SI1010-A-GM Silicon Laboratories Inc, SI1010-A-GM Datasheet - Page 153
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1010-A-GM
Manufacturer Part Number
SI1010-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1010-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
20dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
85mA
Data Interface
PCB, Surface Mount
Memory Size
16kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
20 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1874-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1010-A-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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13.6. Minimizing Flash Read Current
The Flash memory in the Si1010/1/2/3/4/5 devices is responsible for a substantial portion of the total digital
supply current when the device is executing code. Below are suggestions to minimize Flash read current.
1. Use idle, suspend, or sleep modes while waiting for an interrupt, rather than polling the interrupt flag.
2. Si1010/1/2/3/4/5 devices have a one-shot timer that saves power when operating at system clock
3. Flash read current depends on the number of address lines that toggle between sequential Flash read
4. The Flash memory is organized in rows of 64 bytes. A substantial current increase can be detected
5. To minimize the power consumption of small loops, it is best to locate them within a single row, if
6. To write software that is compatible with all devices in the ‘F93x-’F92x and ‘F91x-’F90x product families,
Idle Mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no
more than three system clock cycles. See the Power Management chapter for details on the various
low-power operating modes.
frequencies of 14 MHz or less. The one-shot timer generates a minimum-duration enable signal for the
Flash sense amps on each clock cycle in which the Flash memory is accessed. This allows the Flash to
remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 14 MHz, the system clock cycle becomes short enough that the one-shot
timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces
power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting
the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot, clear the BYPASS bit to logic 0.
operations. In most cases, the difference in power is relatively small (on the order of 5%).
when the read address jumps from one row in the Flash memory to another. Consider a 3-cycle loop
(e.g., SJMP $, or while(1);) which straddles a Flash row boundary. The Flash address jumps from one
row to another on two of every three clock cycles. This can result in a current increase of up 30% when
compared to the same 3-cycle loop contained entirely within a single row.
possible. To check if a loop is contained within a Flash row, divide the starting address of the first
instruction in the loop by 64. If the remainder (result of modulo operation) plus the length of the loop is
less than 63, then the loop fits inside a single Flash row. Otherwise, the loop will be straddling two
adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to
another will occur on relatively few clock cycles, and any resulting increase in operating current will be
negligible.
the Flash row size should be considered 64 bytes.
Rev. 1.0
Si1010/1/2/3/4/5
153
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