AS3977-BQFU austriamicrosystems, AS3977-BQFU Datasheet - Page 27

• Manufacturer Part Number: AS3977-BQFU
• Description: IC RF TRANSMITTER FSK 16-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3977-BQFU

• Frequency: 300MHz ~ 928MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 100 kbps
• Power - Output: 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Current - Transmitting: -

AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
The state can be left at the falling edge of ENABLE, or increasing the Supply Voltage above the threshold and setting
the register bit (LT) to zero. The control of the power amplifier is determined by the command byte (bit A4 and A5).
Table 20. PA Control Modes
ENABLE Signal Functionality
Figure 21
DATAIO.
Table 21. ENABLE Signal Functionality
Communication and Command Byte Structure
A frame consists of a command byte including address/configuration and a following bit stream that can either
represent an integer number of bytes or a random sequence of bits when the command is transmit. Command is
encoded in the 2 first bits, while address is given on 6 bits. In case if the command is neither read nor write, these bits
are used to configure the transmission and they will be stored until the next configuration.
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Active, Transmit
Active, Transmit
Power Down
All States
Transmit
Transmit
Transmit
Transmit
Transmit
State
Mode
State
All
All
summarizes the function of ENABLE in combination with the SDI state and the logical level of CLK and
LT
ENABLE
1
0
0
0
0
↑
↑
↓
↓
0
A4
X
X
0
0
1
CLK
X
0
1
X
X
X
X
X
X
X
A5
X
X
X
0
1
ENABLE
Revision 3.5
X
↓
↓
↓
1
DATAIO
X
X
X
X
X
X
X
X
0
1
PAON high on the subsequent sampling edge of CLK
synchronized with baud rate, DATAIO is latched
PAON low at the falling edge of ENABLE but
PAON low at the falling edge of ENABLE
indicates data are sampled at the falling edge of
indicates data are sampled at the rising edge of
activates the crystal oscillator (PD is set to low)
crystal clock cycles the IC reaches the Power
PAON stays high, DATAIO is latched
(duration: min > 1 SDI CLK cycle, max: < 1/
activates the Power Down Timer; after 2
after receiving the command byte
activates MCCLK, f
MCCLK configuration is unchanged
resets the SDI and state machine
sets DATAIO to high impedance
indicates the end of Read/Write
switches off the PA (if enabled)
resets the Power Down Timer
latches DATAIO (if enabled)
(re-)enters the Active state
disables CLK and DATAIO
sets the lock transmit bit
resets the SDI Interface
Description
PAON low
Description
Down Mode
f
crystal
CLK
CLK
* 2
MCCLK
16
)
=f
XOSC
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