M24LR64-RMB6T/2 STMicroelectronics, M24LR64-RMB6T/2 Datasheet - Page 18
M24LR64-RMB6T/2
Manufacturer Part Number
M24LR64-RMB6T/2
Description
13.56MHZ 64KBIT EEPROM UFDFPN8
Manufacturer
STMicroelectronics
Datasheet
1.M24LR64-RMB6T2.pdf
(128 pages)
Specifications of M24LR64-RMB6T/2
Featured Product
STM32 Cortex-M3 Companion Products
Rf Type
Read / Write
Frequency
13.56MHz
Features
64 Kbit EEPROM
Package / Case
8-MLP, 8-UFDFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10485-2
M24LR64-RMR6T/2
M24LW64-RMB6T/2
M24LR64-RMR6T/2
M24LW64-RMB6T/2
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User memory organization
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User memory organization
The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in
Figure 7
and/or write-protected using a specific password command. Read and write operations are
possible if the addressed data are not in a protected sector.
The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The M24LR64-R includes an AFI register that stores the application family identifier, and a
DSFID register that stores the data storage family identifier used in the anticollision
algorithm.
The M24LR64-R has four additional 32-bit blocks that store an I
password codes.
Figure 6.
shows the memory sector organization. Each sector can be individually read-
Block diagram
AC0
AC1
RF V
RF
CC
Doc ID 15170 Rev 12
Power management
Logic
EEPROM
Latch
Contact V
2
I
2
C password plus three RF
C
CC
ai15123
SCL
SDA
V
V
CC
SS
Table
M24LR64-R
5.
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