M24LR64-RMB6T/2 STMicroelectronics, M24LR64-RMB6T/2 Datasheet - Page 37
M24LR64-RMB6T/2
Manufacturer Part Number
M24LR64-RMB6T/2
Description
13.56MHZ 64KBIT EEPROM UFDFPN8
Manufacturer
STMicroelectronics
Datasheet
1.M24LR64-RMB6T2.pdf
(128 pages)
Specifications of M24LR64-RMB6T/2
Featured Product
STM32 Cortex-M3 Companion Products
Rf Type
Read / Write
Frequency
13.56MHz
Features
64 Kbit EEPROM
Package / Case
8-MLP, 8-UFDFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10485-2
M24LR64-RMR6T/2
M24LW64-RMB6T/2
M24LR64-RMR6T/2
M24LW64-RMB6T/2
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M24LR64-R
6
7
User memory initial state
The device is delivered with all bits in the user memory array set to 1 (each byte contains
FFh).
RF device operation
The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in
sector can be individually read- and/or write-protected using a specific lock or password
command.
Read and Write operations are possible if the addressed block is not protected. During a
Write, the 32 bits of the block are replaced by the new 32-bit value.
The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The M24LR64-R also includes an AFI register in which the application family identifier is
stored, and a DSFID register in which the data storage family identifier used in the
anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which
the password codes are stored.
Doc ID 15170 Rev 12
User memory initial state
Table
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