XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 24

• Manufacturer Part Number: XR20M1172IL32-F
• Description: IC UART FIFO I2C/SPI 64B 32QFN
• Manufacturer: Exar Corporation

Specifications of XR20M1172IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
The M1172 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 19
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during
internal loopback.
2.17
Internal Loopback
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
F
IGURE
19. I
NTERNAL
L
Transmit Shift Register
Receive Shift Register
OOP
B
(RHR/FIFO)
(THR/FIFO)
ACK
RTS#
CTS#
DTR#
DSR#
CD#
RI#
24
M CR bit-4=1
VCC
OP2#
OP1#
VCC
VCC
TX
RX
RTS#
CTS#
DTR#
DSR#
RI#
CD#
REV. 1.0.1