XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 39
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XR20M1172IL32-F
Manufacturer Part Number
XR20M1172IL32-F
Description
IC UART FIFO I2C/SPI 64B 32QFN
Manufacturer
Exar Corporation
Datasheet
1.XR20M1172IG28-F.pdf
(58 pages)
Specifications of XR20M1172IL32-F
Number Of Channels
2, DUART
Package / Case
32-VFQFN Exposed Pad
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
1.62 V ~ 3.63 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
16 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.62 V
Supply Current
250 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
1.62V To 3.63V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR20M1172IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.1
EFCR[7]: IrDA mode
This bit selects between the slow and fast IrDA modes. See
complete details.
•
•
EFCR[6]: Reserved
EFCR[5]: Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Half-Duplex Direction Control output (RTS#). This bit will only
affect the behavior of the RTS# output if EFCR[4] = 1. See
on page 20
•
•
EFCR[4]: Auto RS-485 Enable
This bit enables the RTS# output as the Auto RS-485 Half-Duplex Direction Control output. See
2.14, Auto RS485 Half-duplex Control” on page 20
•
•
EFCR[3]: Reserved
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
•
•
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
•
•
EFCR[0]: 9-bit or Multidrop Mode Enable
This bit enables 9-bit or Multidrop mode. See
for complete details.
•
•
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed.
FRACTIONAL DIVISOR” ON PAGE 13.
4.19
4.20
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps
Logic 0 = RTS# output is LOW when transmitting and HIGH when receiving.
Logic 1 = RTS# output is HIGH when transmitting and LOW when receiving.
Logic 0 = RTS# output can be used for Auto RTS Hardware Flow Control or as a general purpose output.
Logic 1 = RTS# output enabled as the Auto RS-485 Half-Duplex Direction Control output.
Logic 0 = Transmitter is enabled
Logic 1 = Transmitter is disabled
Logic 0 = Receiver is enabled
Logic 1 = Receiver is disabled
Logic 0 = Normal 8-bit mode
Logic 1 = Enable 9-bit or Multidrop mode
Extra Features Control Register (EFCR) - Read/Write
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
for complete details.
“Section 2.14, Auto RS485 Half-duplex Control” on page 20
SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
39
for complete details.
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
“Section 2.14, Auto RS485 Half-duplex Control”
“Section 2.15, Infrared Mode” on page 22
XR20M1172
“Section
for