XR17V352IB113-F Exar Corporation, XR17V352IB113-F Datasheet - Page 9

• Manufacturer Part Number: XR17V352IB113-F
• Description: IC UART PCIE 256B DUAL 113FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB113-F

• Number Of Channels: 2, DUART
• Package / Case: 113-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 113
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
A
O
DDRESS
0x0C
0x00
0x04
0x08
0x10
0x14
FFSET
31:16
15:0
31
30
29:28
27
26:25
24
23
22
21
20
19:16
15:11,
9,7, 5,
4, 3, 2
10
8
6
1
0
31:8
7:0
31:24
23:16
15:8
7:0
31:11
10:0
31:0
B
ITS
EWR
EWR
RWC
RWC
RWR
RWR
RWR
RWR
EWR
RWR
RWR
T
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1: PCI L
Device ID
Vendor ID (Exar) specified by PCISIG
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
Target Abort.
DEVSEL# timing.
Unemployments bus master error reporting bit
Fast back to back transactions are supported
Reserved Status bit
66MHz capable
Capabilities List
Reserved Status bits
Command bits (reserved)
This bit disables the device from asserting INTx#. logic 1 = dis-
able assertion of INTx# and logic 0 = enables assertion of INTx#
SERR# driver enable. logic 1=enable driver and 0=disable driver
Parity error enable. logic 1=respond to parity error and 0=ignore
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
Device’s response to I/O space accesses is disabled.
(0 = disable I/O space accesses)
Class Code (Default is ’Simple 550 Communication Controller’)
Revision ID (Exar device revision number)
BIST (Built-in Self Test)
Header Type (a single function device with one BAR)
Unimplemented Latency Timer (needed only for bus master)
Unimplemented Cache Line Size
Memory Base Address Register (BAR0)
Claims an 2K address space for the memory mapped UARTs
including the UARTs on the expansion interface.
Unimplemented Base Address Register (returns zeros)
OCAL
B
US
C
ONFIGURATION
9
HIGH PERFORMANCE DUAL PCI EXPRESS UART
D
ESCRIPTION
S
PACE
R
EGISTERS
Current Rev. value
(
HEX OR BINARY
XR17V352
R
0x00000000
ESET
0x070002
0x00000
0x0352
0x13A8
0x0000
0x0000
0000b
0x00
0x00
0x00
0x00
00b
00b
0b
0b
0b
0b
0b
0b
0b
1b
0b
0b
0b
0b
0b
V
ALUE
)