XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 51

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
xr
xr
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
ExClk_n pin and output this clock on the RxClk_n output.In Single Frequency Mode (SFM), the clock recovery
locks into the rate clock generated and output this clock on the RxClk_n pins. The data on the RPOS_n and
RNEG_n pins can be forced to zero by pulling the LOSMUT pin “High” (in Hardware Mode) or by setting the
LOSMUT_n bits in the individual channel control register to “1” (in Host Mode).
N
There are three fundamental parameters that describe circuit performance relative to jitter:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification.
F
7.0 JITTER:
7.1
6.4.3
7.1.1
OTE
IGURE
Jitter Tolerance (Receiver)
Jitter Transfer (Receiver/Transmitter)
Jitter Generation
: When the LOS condition is cleared, the recovered data is output on RPOS_n and RNEG_n pins.
22. J
J
ITTER
Muting the Recovered Data with LOS condition:
DS3/STS-1 Jitter Tolerance Requirements:
ITTER
T
OLERANCE
T
Synthesizer
OLERANCE
Generator
Pattern
FREQ
Modulation
- R
Freq.
ECEIVER
M
EASUREMENTS
:
Data
XRT75R03
DUT
48
Clock
Detector
Error
XRT75R03
REV. 1.0.8