XRT75R03IVTR Exar Corporation, XRT75R03IVTR Datasheet - Page 80

• Manufacturer Part Number: XRT75R03IVTR
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRT75R03
REV. 1.0.8
B
IT
N
1
0
UMBER
TxCLKINV
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TxLEV
N
AME
T
R/W
R/W
YPE
D
V
EFAULT
ALUE
0
0
77
Transmit Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of
the TxCLK_n input that the Transmit Section of Channel_n
will use to sample the TPDATA_n and TNDATA_n input
pins, as described below.
0 - Configures the Transmit Section (within the corre-
sponding channel) to sample the TPDATA_n and
TNDATA_n input pins upon the falling edge of TxCLK_n.
1 - Configures the Transmit Section (within the corre-
sponding channel) to sample the TPDATA_n and
TNDATA_n input pins upon the rising edge of TxCLK_n.
N
Transmit Line Build-Out Select - Channel_n:
This READ/WRITE bit-field is used to either enable or dis-
able the Transmit Line Build-Out (e.g., pulse-shaping) cir-
cuit within the corresponding channel. The user should set
this bit-field to either "0" or to "1" based upon the following
guidelines.
0 - If the cable length between the Transmit Output (of the
corresponding Channel) and the DSX-3/STSX-1 location is
225 feet or less.
1 - If the cable length between the Transmit Output (of the
corresponding Channel) and the DSX-3/STSX-1 location is
225 feet or more.
The user must follow these guidelines in order to insure
that the Transmit Section (of Channel_n) will always gen-
erate a DS3 pulse that complies with the Isolated Pulse
Template requirements per Bellcore GR-499-CORE, or an
STS-1 pulse that complies with the Pulse Template
requirements per Telcordia GR-253-CORE.
N
OTE
OTE
:
: This bit-field is ignored if the channel has been
accomplished via the Host Mode, it is done on a
per-channel basis.
configured to operate in the E3 Mode.
Whenever
D
ESCRIPTION
this
configuration
xr
xr
xr
xr
setting
is