MCP4441-502E/ST Microchip Technology, MCP4441-502E/ST Datasheet - Page 56

• Manufacturer Part Number: MCP4441-502E/ST
• Description: IC DGTL POT 129TAPS QUAD 20TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP4441-502E/ST

• Taps: 129
• Resistance (ohms): 5K
• Number Of Circuits: 4
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• End To End Resistance: 5kohm
• Track Taper: Linear
• Resistance Tolerance: ± 20%
• No. Of Steps: 129
• Supply Voltage Range: 2.7V To 5.5V
• Control Interface: I2C
• No. Of Pots: Quad
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP444X/446X
6.2.4
The address byte is the first byte received following the
START condition from the master device. The address
contains four (or more) fixed bits and (up to) three user
defined hardware address bits (pins A1 and A0). These
7-bits address the desired I
address bits are fixed to “01011” and the device
appends the value of following two address pins (A1
and A0).
Since there are address bits controlled by hardware
pins, there may be up to four MCP44XX devices on the
same I
Figure 6-9
contains the seven address bits. There is also a read/
write (R/W) bit.
device.
Hardware Address Pins
The hardware address bits (A1, and A0) correspond to
the logic level on the associated address pins. This
allows up to eight devices on the bus.
These pins have a weak pull-up enabled when the V
< V
technology and exhibits the same characteristics as the
High-voltage tolerant I/O structure.
The state of the A0 address pin is latch on POR/BOR.
This is required since High Voltage commands force
this pin (HVC/A0) to the V
DS22265A-page 56
BOR
2
. The weak pull-up utilizes the “smart” pull-up
C bus.
shows the slave address byte format, which
ADDRESSING
Table 6-2
IHH
shows the fixed address for
level.
2
C device. The A6:A2
DD
FIGURE 6-9:
I
TABLE 6-2:
6.2.5
The MCP44XX implements slope control on the SDA
output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
2
Device
MCP44XX ‘0101 1’b + A1:A0
Note 1:
Start
bit
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
A bit (controlled by slave device)
S A6 A5 A4 A3 A2 A1 A0 R/W A/A
C Control Byte.
“0” “1” “0” “1”
A0 is used for High-Voltage commands
(HVC/A0) and the value is latched at
POR/BOR.
SLOPE CONTROL
Address
Slave Address
DEVICE SLAVE ADDRESSES
Slave Address Bits in the
See
© 2010 Microchip Technology Inc.
“1”
R/W = 0 = write
R/W = 1 = read
R/W bit
Table 6-2
Comment
Supports up to 4
devices.
(Note
1)