XC3S50AN-4TQ144I Xilinx Inc, XC3S50AN-4TQ144I Datasheet - Page 64

• Manufacturer Part Number: XC3S50AN-4TQ144I
• Description: IC FPGA SPARTAN 3AN 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQ144I

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Slave Parallel Mode Timing
X-Ref Target - Figure 15
Table 56: Timing for the Slave Parallel Configuration Mode
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
(Open-Drain)
Notes:
1.
2.
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
RDWR_B
PROG_B
Symbol
The numbers in this table are based on the operating conditions set forth in
Some Xilinx documents refer to Parallel modes as SelectMAP modes.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332, Chapter 7, section “Non-Continuous SelectMAP Data
Loading” for more details.
D0 - D7
(Inputs)
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal
at the CCLK input pin
Figure 15: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
No bitstream compression
With bitstream compression
Description
Byte 0
T
SMCSCC
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
SMCCD
Byte 1
Table
10.
T
T
MCCH
SCCH
1/F
CCPAR
All Speed Grades
Byte n
Min
1.0
15
7
7
0
0
5
5
0
0
T
T
SCCL
T
MCCL
SMCCCS
Byte n+1
Max
80
80
–
–
–
–
–
–
–
–
DS529-3_02_051607
T
SMWCC
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
64