XC3S50AN-4TQ144I Xilinx Inc, XC3S50AN-4TQ144I Datasheet - Page 66

• Manufacturer Part Number: XC3S50AN-4TQ144I
• Description: IC FPGA SPARTAN 3AN 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQ144I

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 58: Configuration Timing Requirements for Attached SPI Serial Flash
Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 17
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
(Open-Drain)
CCS
DSU
DH
V
Symbol
PROG_B
LDC[2:0]
or f
PUDC_B
CSO_B
A[25:0]
These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
CCLK
D[7:0]
R
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
Figure 17: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
Byte 0
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
INITADDR
000_0001
Byte 1
T
AVQV
T
T
Data
T
CCS
DSU
V
f
T

C
New ConfigRate active
DH
T



T
Requirement
CCLK1
Address
MCCLn
T

-------------------------------- -
T
T
T
CCO
CCLKn min
MCCL1
MCCL1
Data
T
T
MCCH1
DCC
1
–

T
T
–
–
Address
CCLKn
DCC
T
T
CCO
CCO

Data
DS557-3_16_032009
Address
T
Data
CCD
Units
MHz
ns
ns
ns
ns
66