XC3S250E-4TQ144I Xilinx Inc, XC3S250E-4TQ144I Datasheet - Page 89

• Manufacturer Part Number: XC3S250E-4TQ144I
• Description: IC FPGA SPARTAN 3E 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4TQ144I

• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 108
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Voltage Compatibility
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage.
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Power-On Precautions if PROM Supply is Last in
Sequence
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
DS312-2 (v3.8) August 26, 2009
Product Specification
CCLK
INIT_B
DONE
PROG_B
V
Pin Name
The FPGA’s parallel Flash interface signals are within
R
FPGA Direction
bidirectional I/O
bidirectional I/O
Open-drain
Open-drain
Output
Input
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long or
has multiple connections, terminate
this output to maintain signal
integrity. See
Considerations.
Initialization Indicator. Active
Low. Goes Low at start of
configuration during the
Initialization memory clearing
process. Released at the end of
memory clearing, when the mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Program FPGA. Active Low. When
asserted Low for 500 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table
a 3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Consequently, in most
78). If driving externally with
Description
CCLK Design
www.xilinx.com
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
FPGA’s other V
quently, there is no issue. However, if the PROM supply is
last in the sequence, a potential race occurs between the
FPGA and the parallel Flash PROM. See
cautions if 3.3V Supply is Last in Sequence
description of the issue for SPI Flash PROMs.
Supported Parallel NOR Flash PROM Densities
Table 60
to program a single Spartan-3E FPGA. Parallel Flash den-
sity is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration, drives
the CCLK inputs of all other
FPGAs in the daisy-chain.
Active during configuration. If CRC
error detected during
configuration, FPGA drives
INIT_B Low.
Low indicates that the FPGA is not
yet configured.
Must be High to allow
configuration to start.
During Configuration
indicates the smallest usable parallel Flash PROM
CCINT
and V
CCAUX
Functional Description
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If unused in the
application, drive INIT_B
High.
Pulled High via external
pull-up. When High,
indicates that the FPGA is
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
After Configuration
supplies, and conse-
Power-On Pre-
for a similar
Table 60
89