XC4VFX12-10SF363I Xilinx Inc, XC4VFX12-10SF363I Datasheet
XC4VFX12-10SF363I
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XC4VFX12-10SF363I Summary of contents
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R DS112 (v3.1) August 30, 2010 General Description Combining Advanced Silicon Modular Block (ASMBL™) architecture with a wide variety of flexible features, the Virtex®-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ...
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... Configurable Logic Blocks (CLBs) (3) Array Logic Device Row x Col Cells Slices XC4VSX25 23,040 10,240 XC4VSX35 34,560 15,360 XC4VSX55 128 x 48 55,296 24,576 XC4VFX12 12,312 5,472 XC4VFX20 19,224 8,544 XC4VFX40 41,904 18,624 XC4VFX60 128 x 52 56,880 25,280 XC4VFX100 160 x 68 94,896 42,176 ...
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R SelectIO Technology • 960 user I/Os • Wide selections of I/O standards from 1.5V to 3.3V • Extremely high-performance - 600 Mb/s HSTL & SSTL (on all single-ended I/ Gb/s LVDS (on all differential I/O ...
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R Architectural Description: Virtex-4 FPGA Array Overview Virtex-4 devices are user-programmable gate arrays with various configurable elements and embedded cores opti- mized for high-density and high-performance system designs. Virtex-4 devices implement the following function- ality: • I/O blocks provide the ...
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R range of signal delays. This is especially useful for synchro- nizing signal edges in source synchronous interfaces. General purpose I/O in select locations (four per bank) are designed to be “regional clock capable” I/O by adding spe- cial hardware ...
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R Virtex-4 FX Family This section briefly describes blocks available only in FX devices. RocketIO Multi-Gigabit Transceiver 8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers (MGTs) capable of running 622 Mb/s – 6.5 Gb/s • Full Clock and Data Recovery ...
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... XC4VLX40 N/A XC4VLX60 N/A XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 N/A XC4VSX35 N/A XC4VSX55 XC4VFX12 N/A 240 N/A XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Notes: 1. All packages are also available in Pb-Free versions (SFG/FFG). 2. Pinouts on all packages (except SF363/SFG363 and FF668/FFG668) are configured using the new, improved SparseChevron pin layout for superior signal integrity ...
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R Virtex-4 Documentation Complete and up-to-date documentation of the Virtex-4 family of FPGAs is available on the Xilinx web site. In addi- tion to the most recent Virtex-4 Family Overview, the follow- ing files are also available for download: Virtex-4 ...
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... R Date Version 03/12/07 2.1 Table XC4VSX25, XC4VSX35, and XC4VFX12 devices. 09/28/07 3.0 All Virtex-4 devices released to Production status. See DS302, Virtex-4 Data Sheet, for full particulars. No changes in this document from previous revision. 08/30/10 3.1 See detailed product revisions. In package column. DS112 (v3.1) August 30, 2010 ...