XC4VFX12 XILINX [Xilinx, Inc], XC4VFX12 Datasheet

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XC4VFX12

Manufacturer Part Number
XC4VFX12
Description
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Virtex-4 User Guide
DS112 (v1.1) September 10, 2004
General Description
The Virtex-4™ Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or
ASMBL™ column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families
(platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of
hard-IP core blocks complete the system solution. These cores include the PowerPC™ processors (with a new APU
interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks,
dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4
building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II,
Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a
state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible
features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC
technology.
Summary of Virtex-4 Features
Table 1: Virtex-4 FPGA Family Members
DS112 (v1.1) September 10, 2004
Advance Product Specification
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VLX100
XC4VLX160
XC4VLX200 192 x 116
Device
Three families LX/SX/FX
-
-
-
Xesium™ Clock Technology
-
-
-
XtremeDSP™ Slice
-
-
-
Smart RAM Memory Hierarchy
-
-
-
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Virtex-4 LX: High-performance logic applications solution
Virtex-4 FX: High-performance, full-featured solution for
embedded platform applications
Virtex-4 SX: High-performance solution for Digital Signal
Processing (DSP) applications
Digital Clock Manager (DCM) blocks
Additional Phase-Matched Clock Dividers (PMCD)
Differential Global Clocks
18x18, two’s complement, signed Multiplier
Optional pipeline stages
Built-In Accumulator (48-bits) & Adder/Subtracter
Distributed RAM
Dual-Port 18-Kbit RAM blocks
·
·
High-speed memory interface support: DDR and DDR-2
SDRAM, QDR-II, RLDRAM-II, and FCRAM-II
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Row x Col
128 x 36
128 x 52
160 x 56
192 x 64
192 x 88
64 x 24
96 x 28
Optional pipeline stages
Optional programmable FIFO logic - Automatically
remaps RAM signals as FIFO signals
Array
Configurable Logic Blocks (CLBs)
110,592
152,064
200,448
13,824
24,192
41,472
59,904
80,640
Logic
Cells
10,752
18,432
26,624
35,840
49,152
67,584
89,088
Slices
6,144
R
Distributed
RAM (Kb)
1056
1392
Max
168
288
416
560
768
96
(1)
Slices
Xtreme
DSP
32
48
64
64
80
96
96
96
(2)
Blocks
18 Kb
160
200
240
288
336
48
72
96
Block RAM
0
0
www.xilinx.com
RAM (Kb)
Block
1,296
1,728
2,880
3,600
4,320
5,184
6,048
Max
0
864
Virtex-4 Family Overview
Advance Product Specification
DCMs PMCDs
12
12
12
12
4
8
8
8
SelectIO Technology
-
-
-
-
Flexible Logic Resources
Built-in System Monitor (voltage/temp. measurement)
10-bit, 200kSPS A/D Converter (ADC)
Secure Chip AES Bitstream Encryption
90-nm copper CMOS process
1.2V core voltage
Flip-Chip Packaging
RocketIO™ 622 Mb/s to 11.1 Gb/s Multi-Gigabit
Transceivers (MGT) (FX only)
IBM PowerPC RISC Processor Core (FX only)
-
-
Multiple Tri-Mode Ethernet MACs (FX only)
1.5 to 3.3 V I/O Operation
Built-In ChipSync™ Source-Synchronous Technology
Digitally-controlled impedance (DCI) active termination
Fine grained I/O banking (Configuration in one bank)
PowerPC 405 (PPC405) Core
Auxiliary Processor Unit Interface (User Coprocessor)
0
4
4
4
8
8
8
8
Monitors
System
0
1
1
1
1
1
1
1
Blocks
ADC
0
0
0
0
1
1
1
1
Processor
PowerPC
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ethernet
MACs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Transciever
RocketIO
Blocks
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Banks
Total
I/O
11
13
13
15
17
17
17
9
User
Max
320
448
640
640
768
960
960
960
I/O
21

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XC4VFX12 Summary of contents

Page 1

Virtex-4 User Guide R DS112 (v1.1) September 10, 2004 General Description The Virtex-4™ Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or ASMBL™ column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs ...

Page 2

... Slices Device Row x Col Cells Distributed RAM (Kb) XC4VSX25 23,040 10,240 XC4VSX35 34,560 15,360 XC4VSX55 128 x 48 55,296 24,576 XC4VFX12 12,312 5,472 XC4VFX20 19,224 8,544 XC4VFX40 41,904 15,552 XC4VFX60 128 x 52 56,880 25,280 XC4VFX100 160 x 68 94,896 ...

Page 3

R SelectIO Technology • 960 user I/Os • Wide selections of I/O standards from 1.5V to 3.3V • Extremely high-performance - 600 Mb/s HSTL & SSTL (on all single-ended I/ Gb/s LVDS (on all differential I/O ...

Page 4

Virtex-4 Family Overview Tri-mode Ethernet Media Access Controller • IEEE 802.3 compliant • Operates at 10, 100, and 1,000 Mb/s • Supports tri-mode auto-detect • Receive address filter (16 address entries) • Fully monolithic 1000Base-X solution with RocketIO MGT • ...

Page 5

R Virtex-4 Features This section briefly describes the features of the Virtex-4 family of FPGAs. Input/Output Blocks (SelectIO) IOBs are programmable and can be categorized as follows: • Programmable single-ended or differential (LVDS) operation • Input block with an optional ...

Page 6

Virtex-4 Family Overview XtremeDSP Slices The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s complement signed multiplier, adder logic, and a 48-bit accumulator. Each multiplier or accumulator can be used independently. These blocks are designed to implement extremely efficient ...

Page 7

R One or Two PowerPC 405 Processor Cores • 32-bit Harvard Architecture • 5-Stage Execution Pipeline • Integrated 16KB Level 1 Instruction Cache and 16KB Level 1 Data Cache - Integrated Level 1 Cache Parity Generation and Checking • CoreConnect™ ...

Page 8

... MGTs I/O MGTs XC4VLX15 N/A 240 XC4VLX25 N/A 240 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 (1) XC4VFX12 N/A 240 (1) XC4VFX20 8 (1) XC4VFX40 12 (1) XC4VFX60 12 (1) XC4VFX100 (1) XC4VFX140 Notes: 1. These package/part combinations and the quantity of MGTs and I/Os are not final numbers. Virtex-4 Ordering Information ...

Page 9

R Revision History The following table shows the revision history for this document. Date Version 08/02/04 1.0 Initial Xilinx release. Printed Handbook version. 09/10/04 1.1 Typographical edits. Virtex-4 Documentation Complete and up-to-date documentation of the Virtex-4 family of FPGAs is ...

Page 10

Virtex-4 Family Overview 30 www.xilinx.com R DS112 (v1.1) September 10, 2004 Advance Product Specification ...

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