M058LAN Nuvoton Technology Corporation of America, M058LAN Datasheet - Page 220
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M058LAN
Manufacturer Part Number
M058LAN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro M051™r
Specifications of M058LAN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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NuMicro M051
CAPCH1EN
CFL_IE1
CRL_IE1
INV1
Reserved
CFLRI0
CRLRI0
Reserved
CAPIF0
Capture PWM Group Channel 1 transition Enable/Disable
1 = Enable capture function on PWM group channel 1.
0 = Disable capture function on PWM group channel 1
When Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch)
and CFLR (Falling latch).
When Disable, Capture does not update CRLR and CFLR, and disable PWM group
channel 1 Interrupt.
PWM Group Channel 1 Falling Latch Interrupt Enable
1 = Enable falling latch interrupt
0 = Disable falling latch interrupt
When Enable, if Capture detects PWM group channel 1 has falling transition, Capture
issues an Interrupt.
PWM Group Channel 1 Rising Latch Interrupt Enable
1 = Enable rising latch interrupt
0 = Disable rising latch interrupt
When Enable, if Capture detects PWM group channel 1 has rising transition, Capture
issues an Interrupt.
PWM Group Channel 1 Inverter ON/OFF
1 = Inverter ON. Reverse the input signal from GPIO before fed to Capture timer
0 = Inverter OFF
Reserved
CFLR0 Latched Indicator Bit
When PWM group input channel 0 has a falling transition, CFLR0 was latched with
the value of PWM down-counter and this bit is set by hardware.
Clear this bit by writing a one to it.
CRLR0 Latched Indicator Bit
When PWM group input channel 0 has a rising transition, CRLR0 was latched with
the value of PWM down-counter and this bit is set by hardware.
Clear this bit by writing a one to it.
Reserved
Capture0 Interrupt Indication Flag
If PWM group channel 0 rising latch interrupt is enabled (CRL_IE0=1), a rising
transition occurs at PWM group channel 0 will result in CAPIF0 to high; Similarly, a
falling transition will cause CAPIF0 to be set high if PWM group channel 0 falling
latch interrupt is enabled (CFL_IE0=1). This flag is clear by software with a write 1 to
™
Series Technical Reference Manual
- 220 -
Publication Release Date: Sep 14, 2010
Revision V1.2
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