ATTINY9-MAH Atmel, ATTINY9-MAH Datasheet - Page 9
ATTINY9-MAH
Manufacturer Part Number
ATTINY9-MAH
Description
IC MCU AVR 1K FLASH 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY9-MAH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-MAHR
Manufacturer:
ST
Quantity:
101
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4.5
4.6
8127D–AVR–02/10
Stack Pointer
Instruction Execution Timing
Figure 4-3.
In different addressing modes these address registers function as automatic increment and
automatic decrement (see document “AVR Instruction Set” and section
mary” on page 152
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x40. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
X-register
Y-register
Z-register
The X-, Y-, and Z-registers
for details).
15
7
15
7
15
7
CPU
R27
R29
R31
XH
YH
ZH
, directly generated from the selected clock source for the
0
0
0
7
7
7
ATtiny4/5/9/10
“Instruction Set Sum-
XL
YL
ZL
R26
R28
R30
0
0
0
0
0
0
9
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