ATMEGA165P-16MNR Atmel, ATMEGA165P-16MNR Datasheet - Page 187
ATMEGA165P-16MNR
Manufacturer Part Number
ATMEGA165P-16MNR
Description
IC MCU AVR 16K 16MHZ 64MLF
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165P-16MNR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.11.5
8019K–AVR–11/10
UBRRnL and UBRRnH – USART Baud Rate Registers
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 18-12. UCPOLn Bit Settings
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRnH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four
most significant bits, and the UBRRnL contains the eight least significant bits of the USART
baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud
rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.
Bit
(0xC5)
(0xC4)
Read/Write
Initial Value
UCPOLn
0
1
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
R/W
15
R
–
7
0
0
R/W
14
R
–
6
0
0
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRRn[7:0]
R/W
R/W
11
3
0
0
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
10
2
0
0
UBRRn[11:8]
R/W
R/W
ATmega165P
9
1
0
0
R/W
R/W
8
0
0
0
UBRRnH
UBRRnL
187
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