ATMEGA64L-8AQR Atmel, ATMEGA64L-8AQR Datasheet
ATMEGA64L-8AQR
Specifications of ATMEGA64L-8AQR
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ATMEGA64L-8AQR Summary of contents
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... Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for ATmega64L – 4.5V - 5.5V for ATmega64 • Speed Grades – MHz for ATmega64L – MHz for ATmega64 ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller ...
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Pin Configuration Figure 1. Pinout ATmega64 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Disclaimer Typical ...
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Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits ...
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ATmega103 By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103 Compatibility Mode regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new fea- tures in ATmega64 are not available in this compatibility ...
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Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins ...
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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in 52. Shorter pulses are not guaranteed ...
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... Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega64( ...
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Register Summary Address Name Bit 7 (0xFF) Reserved – .. Reserved – (0x9E) Reserved – (0x9D) UCSR1C – (0x9C) UDR1 (0x9B) UCSR1A RXC1 (0x9A) UCSR1B RXCIE1 (0x99) UBRR1L (0x98) UBRR1H – (0x97) Reserved – (0x96) Reserved – (0x95) UCSR0C – ...
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Register Summary (Continued) Address Name Bit 7 (0x60) Reserved – 0x3F (0x5F) SREG I 0x3E (0x5E) SPH SP15 0x3D (0x5D) SPL SP7 0x3C (0x5C) XDIV XDIVEN 0x3B (0x5B) Reserved – 0x3A (0x5A) EICRB ISC71 0x39 (0x59) EIMSK INT7 0x38 (0x58) ...
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Register Summary (Continued) Address Name Bit 7 0x00 (0x20) PINF PINF7 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status ...
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Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate LD Rd, X Load ...
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Instruction Set Summary (Continued) CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega64( ← None (see specific descr. for Sleep function) None (see specific ...
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... Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2490QS–AVR–07/10 (2) (1) Ordering Code Package ATmega64L-8AU 64A ATmega64L-8MU 64M1 ATmega64-16AU 64A ATmega64-16MU 64M1 Package Type ATmega64(L) Operation Range Industrial ° ...
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Packaging Information 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2490QS–AVR–07/10 ...
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Errata The revision letter in this section refers to the revision of the ATmega64 device. ATmega64, rev. A • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer ...
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Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL reg- ister, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior ...
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Datasheet Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Revision History Changes from Rev. 1. Changed “Low” into “Ext” in 2490P-07/09 ...
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Changes from Rev. 1. Updated 2490J-03/ Added Rev. 2490K-04/06 3. Added Addresses in Register Descriptions. 4. Updated 5. Updated Register- and bit names in 6. Updated note in 7. Updated Features in Changes from Rev. 1. MLF-package alternative ...
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Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04 Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03 Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03 Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03 ATmega64(L) 22 12. Updated features in“Analog to Digital Converter” on page 230 ...
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Added section 11. Changed V 12. Added information about conversion time for Differential mode with Auto Triggering on 13. Added t 14. Updated Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2490B-09/02 to ...
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In the data sheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “OSCCAL – Oscillator Calibration Register(1)” ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...