ATmega64 Atmel Corporation, ATmega64 Datasheet
ATmega64
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ATmega64 Summary of contents
Page 1
... Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V for Atmel ATmega64L – 4.5V - 5.5V for Atmel ATmega64 • Speed Grades – MHz for ATmega64L – MHz for ATmega64 ® 8-bit Microcontroller (1) 8-bit Microcontroller with 64K Bytes In-System Programmable ...
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... Pin Configuration Figure 1. Pinout ATmega64 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology ...
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... Overview The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
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... ATmega103, all I/O locations present in ATmega103 have the same location in Compatibility ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (that is, in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega64 as listed on 74. 2490Q–AVR–06/10 ...
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... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega64 as listed on 81. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter ...
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... The pullup is shown in “DC Characteristics” on page 2490Q–AVR–06/10 , even if the ADC is not used. If the ADC is used, it should be connected Figure 22 on page 52 325. PEN has no function during normal operation. ATmega64(L) Table 19 on page CC and its value is given in Section 7 ...
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... A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2490Q–AVR–06/10 1. ATmega64(L) 8 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2490Q–AVR–06/10 ATmega64(L) 9 ...
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... Space addressing – enabling efficient address calculations. One of the these address pointers 2490Q–AVR–06/10 Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega64(L) Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit ...
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... The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses which can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ALU – ...
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... Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2490Q–AVR–06/ R/W R/W R/W R/W R ⊕ V ATmega64( SREG R/W R/W R ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4, each register is also assigned a data memory address, mapping them ATmega64(L) 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R directly generated from the selected clock source for the CPU ATmega64(L) Figure R26 (0x1A R28 (0x1C R30 (0x1E SP10 SP9 SP8 SPH SP3 SP2 SP1 ...
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... Register File single clock cycle an ALU T1 clk CPU Total Execution Time Result Write Back for details. “Boot Loader Support – Read-While-Write Self-programming” on page ATmega64( “Memory Program- “Interrupts” on page 61. The list also “ ...
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... EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2490Q–AVR–06/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ ATmega64(L) 16 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2490Q–AVR–06/10 ; set global interrupt enable ATmega64(L) 17 ...
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... Boot Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega64 Pro- gram Counter (PC bits wide, thus addressing the 32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
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... Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used. The Extended I/O space does not exist when the ATmega64 is in the ATmega103 compatibility mode. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and the 4,096 bytes of internal data SRAM in the ATmega64 are all accessible through all these addressing modes. The Register File is described in 13. ...
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... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega64 contains 2 Kbytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...
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... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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... EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. 2490Q–AVR–06/10 ATmega64(L) “Boot Loader for details about Boot Table 2 lists the typical pro- ...
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... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega64(L) Typ Programming Time 8448 8 ...
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... Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; ATmega64(L) 25 ...
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... I/O Memory The I/O space definition of the ATmega64 is shown in All ATmega64 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Lower Sector SRW01 SRW00 SRL[2..0] Upper Sector SRW11 SRW10 0xFFFF 1. ATmega64 in non ATmega103 compatibility mode: Memory Configuration A is available (Mem- ory Configuration B N/A). ATmega64 in mega103 compatibility mode: Memory Configuration B is available (Memory Configuration A N/A). ATmega64(L) Figure 1 on page 85). The memory configuration is (1) Memory Configuration B ...
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... The external memory section cannot be divided into sectors with different wait-state settings. • Bus Keeper is not available. • RD, WR, and ALE pins are output only (Port G in ATmega64). Using the External The interface consists of: Memory Interface • AD7:0: Multiplexed low-order address bus and data bus. ...
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... The most important parameters are the access time for the external memory compared to the set-up requirement of the ATmega64. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus ...
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... DA7:0 (XMBK = 1) Prev. Data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). ATmega64(L) ( Address Address XX Data ...
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... DA7:0 (XMBK = 1) Prev. Data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). ATmega64( Address Data Data Data ...
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... SRW11 and SRW10 bits. 2490Q–AVR–06/ SRE SRW10 SE SM1 R/W R/W R – SRL2 SRL1 SRL0 R R/W R/W R ATmega64( SM0 SM2 IVSEL IVCE R/W R/W R/W R SRW01 SRW00 SRW11 – R/W R/W R/W ...
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... Wait two cycles during read/write and wait one cycle before driving out 1 new address (lower/upper sector). For further details of the timing and wait states of the External Memory Interface, see 13 to Figure 16 how the setting of the SRW bits affects the timing. ATmega64(L) Figure 33 ...
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... Kbytes space Address high bits ATmega64( – XMM2 XMM1 XMM0 XMCRB R R/W R/W R Table 5. As described in 36 possible to use the XMMn Released Port Pins None PC7 ...
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... Memory Configuration A AVR Memory Map External 32K SRAM 0x0000 Internal Memory 0x10FF 0x1100 External 0x7FFF 0x8000 Memory 0x90FF 0x9100 (Unused) 0xFFFF ATmega64(L) Figure 17. Memory configuration B Memory Configuration B AVR Memory Map 0x0000 0x0000 Internal Memory 0x0FFF 0x1000 0x10FF 0x1100 External 0x7FFF 0x7FFF ...
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... PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) sts XMCRB, r16 ; store 0x55 to address (OFFSET + external memory ldi r16, 0x55 0x0001+OFFSET, r16 sts (1) 1. See “About Code Examples” on page 9. ATmega64(L) Figure 11, only 60 36 ...
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... AVR Clock I/O Control Unit clk ASY Clock Multiplexer Timer/Counter External RC External Clock Oscillator Oscillator is halted, enabling TWI address reception in all sleep modes. I/O ATmega64(L) CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source Clock Watchdog Clock Watchdog ...
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... Table 7. Number of Watchdog Oscillator Cycles Typ Time-out (V 2490Q–AVR–06/10 (1) 1. For all fuses “1” means unprogrammed while “0” means programmed. 340. = 5.0V) Typ Time-out ( ATmega64(L) CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3.0V) Number of Cycles CC 4.3 ms ...
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... When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail. ATmega64( ...
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... C2 C1 Frequency Range CKSEL3..1 (MHz) (1) 101 0.4 - 0.9 110 0.9 - 3.0 111 3.0 - 8.0 101, 110, 111 1 This option should not be used with crystals, only with ceramic resonators. ATmega64(L) XTAL2 XTAL1 GND Table 8. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – Table 40 ...
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... CC ( 4 32K These options should only be used if frequency stability at start-up is not important for the application. ATmega64(L) Additional Delay from Reset (V = 5.0V) Recommended Usage CC Ceramic resonator, fast 4.1 ms rising power Ceramic resonator slowly rising power Ceramic resonator, BOD – ...
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... Power-down and from Reset Power-save ( This option should not be used when operating close to the maximum frequency of the device. ATmega64(L) XTAL2 XTAL1 GND Frequency Range (MHz) 0.1 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 12.0 = 5.0V) Recommended Usage – BOD enabled Fast rising power ...
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... The device is shipped with this option selected CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value 1. The OSCCAL Register is not available in ATmega103 compatibility mode. ATmega64(L) Table 13. If selected, it will operate and Temperature. When this Oscillator is CC Nominal Frequency (MHz) 1.0 2.0 4.0 8.0 Reset (V = 5.0V) Recommended Usage CC – ...
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... Nominal Frequency (%) 50 75 100 EXTERNAL CLOCK SIGNAL Start-up Time from Power- Additional Delay from down and Power-save Reset ( Reserved ATmega64(L) Table 15. Max Frequency in Percentage of Nominal Frequency (%) 100 150 200 = 5.0 V) Recommended Usage CC – BOD enabled 4.1 ms Fast rising power 65 ms ...
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... Applying an external clock source to TOSC1 is not recommended. Note: 2490Q–AVR–06/10 The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega64(L) 45 ...
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... Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the six available sleep modes as shown in Table 17. Sleep Mode Select SM2 Note: 2490Q–AVR–06/10 presents the different clock systems in the ATmega64, and their distribu SRE SRW10 SE SM1 R/W R/W R/W R/W 0 ...
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... Timer/Counter0 if clocked asynchronously. 2490Q–AVR–06/10 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page , allowing operation only of asynchronous ASY ATmega64(L) , and clk- , while allowing the CPU FLASH “External Interrupts” on page 90 38. 47 ...
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... External Crystal or resonator selected as clock source bit in ASSR is set. 3. Only INT3:0 or level interrupt INT7:4. 2490Q–AVR–06/10 Oscillators ( ( (2) ( (2) ( ATmega64(L) Wake Up Sources ( ( ( (3) ( ...
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... ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 70 /2, the input buffer will use excessive power. CC ATmega64(L) “Analog to Digital Converter” on page 230 for details on how to configure the Ana- for details on how to “Internal Voltage Refer- ) are stopped, the input buffers of the ...
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... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 2490Q–AVR–06/10 ATmega64(L) 50 ...
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... CKSEL Fuses. The different selections for the delay period are presented in Reset Sources The ATmega64 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... BODLEVEL = 0 Minimum low voltage BODLEVEL = 1 period for Brown-out BODLEVEL = 0 Detection Brown-out Detector hysteresis 1. The Power-on Reset will not work unless the supply voltage has been below V ATmega64(L) DATA BUS MCU Control and Status Register (MCUCSR) Brown-Out Delay Counters CK TIMEOUT Min Typ Max 1 ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=1 for ATmega64L and BODLEVEL=0 for ATmega64. BODLEVEL=1 is not appli- cable for ATmega64. Table 19. The POR is activated whenever V rise ...
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... Time-out period t Figure 25. External Reset during Operation Brown-out Detection ATmega64 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...
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... Watchdog Timer JTD – – JTRF R R Only EXTRF and PORF are available in mega103 compatibility mode. ATmega64( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description . Refer to TOUT 55 ...
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... MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Internal Voltage ATmega64 features an internal bandgap reference. This reference is used for Brown-out Detec- tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference Reference to the ADC is generated from the internal bandgap reference ...
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... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega64 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Oscillator Cycles 0 0 16K (16,384 32K (32,768 64K (65,536 128K (131,072 256K (262,144 512K (524,288 1,024K (1,048,576 2,048K (2,097,152) ATmega64(L) Typical Time-out Typical Time-out 3. 5. 17.1 ms 16.3 ms 34.3 ms 32 0.14 s 0.13 s 0.27 s 0.26 s 0.55 s 0.52 s 1.1 s 1.0 s 2.2 s 2.1 s ...
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... Write logical one to WDCE and WDE ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ _WDRC(); /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega64(L) 59 ...
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... WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 2490Q–AVR–06/10 ATmega64(L) page 57 (WDE bit description) must be followed. 60 ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega64. For a general explanation of the AVR interrupt handling, refer to page 15. Interrupt Vectors Table 23. Reset and Interrupt Vectors in ATmega64 Vector No ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 24. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega64 is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E ...
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... Enable interrupts <instr> xxx ... ... ... Comments r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx jmp EXT_INT0 ; IRQ0 Handler jmp EXT_INT1 ; IRQ1 Handler ... ... ; jmp SPM_RDY ; Store Program Memory Ready Handler ATmega64(L) 63 ...
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... SPM_RDY ; Store Program Memory Ready Handler r16,high(RAMEND); Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16,low(RAMEND) out SPL,r16 sei ; Enable interrupts <instr> xxx SRE SRW10 SE SM1 SM0 R/W R/W R/W R/W R ATmega64( SM2 IVSEL IVCE MCUCR R/W R/W R ...
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... Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to boot Flash section */ MCUCR = (1<<IVSEL); ATmega64(L) “Boot Loader Support – Read-While-Write “Boot Loader Support – Read-While- for details on Boot Lock bits. 65 ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O Ports” on page 71. Refer to the individual module sections for a full description of the alternate ATmega64(L) Figure 29. Refer to “Electrical Charac Logic See Figure "General Digital I/O" for Details 87 ...
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... SLEEP: SLEEP CONTROL clk : I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 87, the DDxn bits are accessed at the DDRx I/O address, the ATmega64( DDxn Q CLR RESET Q D PORTxn ...
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... Output 1 X Output Figure 30, the PINxn Register bit and the preceding latch consti- and t pd,max SYSTEM CLK XXX SYNC LATCH PINxn r17 ATmega64(L) Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 69
... The out instruction sets the “SYNC LATCH” signal at the positive edge of the through the synchronizer is one system clock period. pd SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega64( single signal transition on the pin will be delayed 0xFF nop in r17, PINx 0x00 t pd 0xFF ...
Page 70
... Figure 30, the digital input signal can be clamped to ground at the input of the /2. CC “Alternate Port Functions” on page ATmega64(L) 71. 70 ...
Page 71
... PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally in ATmega64(L) Figure 30 can be overridden by alternate ...
Page 72
... This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally TSM – – – ACME R R for more details about this feature. ATmega64( PUD PSR0 PSR321 SFIOR R/W R/W R “Con- 72 ...
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... WR | ADA SRE SRE A7 • ADA | D7 A6 • ADA | D6 OUTPUT • WR OUTPUT • INPUT D6 INPUT – – ATmega64(L) PA5/AD5 PA4/AD4 SRE SRE ~(WR | ADA) • ~(WR | ADA) • PORTA5 • PUD PORTA4 • PUD SRE SRE WR | ADA WR | ADA SRE SRE A5 • ADA | D5 A4 • ...
Page 74
... OC0 (Output Compare and PWM Output for Timer/Counter0) MISO (SPI Bus Master Input/Slave Output) MOSI (SPI Bus Master Output/Slave Input) SCK (SPI Bus Serial Clock) SS (SPI Slave Select input) 1. OC1C not applicable in ATmega103 compatibility mode. ATmega64(L) (1) PA1/AD1 PA0/AD0 SRE ~(WR | ADA) • ...
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... Figure 33 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2490Q–AVR–06/10 and Table 32 relate the alternate functions of Port B to the overriding signals shown in 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, ATmega64(L) 75 ...
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... SPE • MSTR SPE • MSTR 0 0 SPE • MSTR SPE • MSTR SPI SLAVE OUTPUT SPI MSTR OUTPUT SPI MSTR INPUT SPI SLAVE INPUT – – ATmega64(L) PB5/OC1A PB4/OC0 OC1A ENABLE OC0 ENABLE OC1A OC0B 0 ...
Page 77
... SRE • (XMM< SRE • (XMM<1) SRE • (XMM<2) A11 A10 – – – – ATmega64(L) PC5/A13 PC4/A12 SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< SRE • (XMM<3) SRE • (XMM< ...
Page 78
... Interrupt2 Input or UART1 Receive Pin) (1) INT1/SDA (External Interrupt1 Input or TWI Serial DAta) (1) INT0/SCL (External Interrupt0 Input or TWI Serial CLock) 1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode. ATmega64(L) (1) PC1/A9 PC0/A8 SRE • (XMM<7) SRE • (XMM< SRE • (XMM<7) SRE • ...
Page 79
... I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than the input signal, and the pin is driven by an open drain driver with slew-rate limitation. Table 37 Figure 33 on page 2490Q–AVR–06/10 and Table 38 relates the alternate functions of Port D to the overriding signals shown in 71. ATmega64(L) 79 ...
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... When enabled, the Two-wire Serial Interface enables Slew-rate controls on the output pins PD0 and PD1. This is not shown on the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega64(L) PD5/XCK1 PD4/ICP1 ...
Page 81
... Output A for Timer/Counter3) (1) AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output) PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PDI/RXD0 (Programming Data Input or UART0 Receive Pin) 1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility mode. ATmega64(L) Table 39. 81 ...
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... PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data output. During Serial Program Downloading, this pin is used as data output line for the ATmega64. TXD0, UART0 Transmit Pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data input. During serial program downloading, this pin is used as data input line for the ATmega64 ...
Page 83
... ADC5/TMS (ADC input channel 5 or JTAG Test mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test Clock) ADC3 (ADC input channel 3) ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) ATmega64(L) PE1/PDO/TXD0 PE0/PDI/RXD0 TXEN0 RXEN0 0 PORTE0 • PUD ...
Page 84
... PF7/ADC7/TDI PF6/ADC6/TDO JTAGEN JTAGEN 1 0 JTAGEN JTAGEN 0 SHIFT_IR + SHIFT_DR 0 JTAGEN 0 TDO JTAGEN JTAGEN 0 0 – – TDI/ADC7 INPUT ADC6 INPUT ATmega64( PF5/ADC5/TMS PF4/ADC4/TCK JTAGEN JTAGEN 1 1 JTAGEN JTAGEN JTAGEN JTAGEN 0 0 – – TMS/ADC5 TCKADC4 INPUT ...
Page 85
... ADC3 INPUT ADC2 INPUT Alternate Function TOSC1 (RTC Oscillator Timer/Counter0) TOSC2 (RTC Oscillator Timer/Counter0) ALE (Address Latch Enable to external memory) RD (Read strobe to external memory) WR (Write strobe to external memory) ATmega64(L) PF1/ADC1 PF0/ADC0 ...
Page 86
... Port G to the overriding signals shown in 71. PG4/TOSC1 PG3/TOSC2 AS0 AS0 0 0 AS0 AS0 AS0 AS0 0 0 – – T/C0 OSC INPUT T/C0 OSC OUTPUT ATmega64(L) PG2/ALE PG1/RD SRE SRE 0 0 SRE SRE 1 1 SRE SRE ALE – – – – PG0/WR ...
Page 87
... N/A N/A N/A N PORTC7 PORTC6 PORTC5 PORTC4 R/W R/W R/W R DDC7 DDC6 DDC5 DDC4 R/W R/W R/W R ATmega64( PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R PINA3 PINA2 PINA1 PINA0 ...
Page 88
... R/W R/W R/W R PINE7 PINE6 PINE5 PINE4 N/A N/A N/A N PORTF7 PORTF6 PORTF5 PORTF4 R/W R/W R/W R ATmega64( PINC3 PINC2 PINC1 PINC0 N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 ...
Page 89
... R R – – – DDG4 R – – – PING4 N/A ATmega64( DDF3 DDF2 DDF1 DDF0 R/W R/W R/W R PINF3 PINF2 PINF1 PINF0 N/A N/A N/A N PORTG2 PORTG1 ...
Page 90
... If the level is sampled twice by the Watchdog Oscillator clock but ISC31 ISC30 ISC21 ISC20 R/W R/W R/W R Table 48. Edges on INT3..INT0 are registered asynchro- ATmega64(L) 37. Low level interrupts and the 325. The MCU will “Clock Systems and ISC11 ISC10 ISC01 ISC00 EICRA R/W R/W R/W R ...
Page 91
... The rising edge between two samples of INTn generates an interrupt request When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. ATmega64(L) Condition Min Typ Max ...
Page 92
... INT7 INT6 INT5 INT4 INT3 R/W R/W R/W R/W R INTF7 INTF6 INTF5 INTF4 INTF3 R/W R/W R/W R/W R for more information. ATmega64( INT2 INT1 INT0 EIMSK R/W R/W R INTF2 INTF1 INTF0 EIFR R/W R/W R “Digital Input 92 ...
Page 93
... Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn Synchronized Status Flags Status Flags ASSRn Asynchronous Mode Select (ASn) ATmega64(L) Figure 34. For the actual place- 2. CPU accessible I/O Registers, including 104. TOVn (Int. Req.) clk Tn TOSC1 T/C Oscillator Prescaler TOSC2 clk OCn I/O (Int ...
Page 94
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T0 107. For details on clock sources and prescaler, see 110. ATmega64(L) See “Output . When the AS0 I/O “ASSR 94 ...
Page 95
... present or not. A CPU write overrides (has priority over) all counter clear or T0 98. can be used for generating a CPU interrupt. TOV0 98). Figure 36 shows a block diagram of the Output Compare unit. ATmega64(L) T/C clk Tn Oscillator Prescaler clk I/O (“Modes of Oper- Figure TOSC1 ...
Page 96
... Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. 2490Q–AVR–06/10 DATA BUS OCRn TCNTn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega64(L) OCFn (Int.Req.) OCxy 96 ...
Page 97
... COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 104. Table 53 on page 105. For fast PWM mode, refer to Table 55 on page ATmega64(L) Figure 37 shows a simplified sche OCn Pin OCn PORT ...
Page 98
... CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current 2490Q–AVR–06/10 97.). “Timer/Counter Timing Diagrams” on page Figure ATmega64(L) 102. 38. The counter value (TCNT0) OCn Interrupt Flag Set (COMn1 ...
Page 99
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0. 2490Q–AVR–06/10 f clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Figure 39. The TCNT0 value is in the timing diagram shown as a histo- ATmega64( OC0 clk_I ...
Page 100
... OCnPWM ⋅ N 256 = f oc0 clk_I/O ATmega64(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 Table 54 on page 105). The actual OC0 /2 when OCR0 is set to zero. This fea- 100 ...
Page 101
... Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements. 2490Q–AVR–06/ Table 55 on page ATmega64(L) Figure 40. OCn Interrupt Flag Set OCRn Update TOVn Interrupt ...
Page 102
... Timer/Counter operation. The Timer/Counter contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega64(L) f clk_I/O = ----------------- - ⋅ N 510 Figure 40. When the OCR0 value is MAX the ) is therefore shown as a clock enable signal ...
Page 103
... I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega64(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRn + 2 BOTTOM + 1 103 ...
Page 104
... The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 53 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a ATmega64( ...
Page 105
... A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See 101 for more details. ATmega64(L) (1) “Fast PWM Mode” on page 99 (1) “Phase Correct PWM Mode” on page ...
Page 106
... T0S 1 0 clk /256 (From prescaler clk /1024 (From prescaler TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R ATmega64( TCNT0 R/W R/W R/W R OCR0 R/W R/W R/W R Table 106 ...
Page 107
... To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB. 5. Clear the Timer/Counter0 interrupt flags. 6. Enable interrupts, if needed. 2490Q–AVR–06/ – – – – AS0 R ATmega64( TCN0UB OCR0UB TCR0UB ASSR When AS0 is I/O 107 ...
Page 108
... TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as follows: 2490Q–AVR–06/10 ATmega64(L) ) again becomes active, TCNT0 will read as the previous I/O 108 ...
Page 109
... OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed. 2490Q–AVR–06/ OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R/W R ATmega64( TOIE1 OCIE0 TOIE0 TIMSK R/W R/W R/W R TOV1 OCF0 TOV0 TIFR R/W R/W R 109 ...
Page 110
... AS0 PSR0 CS00 CS01 CS02 TIMER/COUNTER0 CLOCK SOURCE . By setting the AS0 bit in ASSR, Timer/Counter0 is asynchronously clocked OSC /256, and clk /1024. Additionally, clk T0S T0S ATmega64(L) 10-BIT T/C PRESCALER 0 clk T0 . clk is by default connected to the main T0S T0S /8, clk /32, clk T0S T0S as well as 0 (stop) may be selected ...
Page 111
... The bit will not be cleared by hardware if the TSM bit is set. 2490Q–AVR–06/ TSM – – – R ATmega64( ACME PUD PSR0 PSR321 SFIOR R/W R/W R/W R 111 ...
Page 112
... However, when using the register or bit defines in a program, the precise form must be used (that is, TCNT1 for accessing Timer/Counter1 counter value and so on). The physical I/O Register and bit locations for ATmega64 are listed in the tion” on page A simplified block diagram of the 16-bit Timer/Counter is shown in I/O Registers, including I/O bits and I/O pins, are shown in bold. 2490Q– ...
Page 113
... Count Clear Control Logic Direction Timer/Counter TCNTx = OCRxA = OCRxB = OCRxC ICRx TCCRxA 1. Refer to Figure 1 on page 2, Timer/Counter1 and 3 pin placement and description. ATmega64(L) (1) TOVx (Int.Req.) Clock Select TCLK Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCFxA (Int.Req.) Waveform Generation OCFxB Fixed (Int ...
Page 114
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega64(L) (See 114 ...
Page 115
... Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into TCNTn; ... 1. See “About Code Examples” on page 9. ATmega64(L) 115 ...
Page 116
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 9. The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega64(L) 116 ...
Page 117
... SREG = sreg; 1. See “About Code Examples” on page 9. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNTn. “Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. ATmega64(L) 144. 117 ...
Page 118
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega64(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 124 ...
Page 119
... ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3. ATmega64(L) Figure (1) DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise ...
Page 120
... I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). 2490Q–AVR–06/10 115. ATmega64(L) “Accessing 16-bit Registers” (Figure 59 on page 144). The edge detector is also 120 ...
Page 121
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega64(L) 124.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 122
... PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin System Reset occur, the OCnx Register is reset to “0”. 2490Q–AVR–06/10 115. ATmega64(L) “Accessing 16-bit Registers” Figure 50 shows a simplified 122 ...
Page 123
... A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 2490Q–AVR–06/10 Waveform Generator I/O See “16-bit Timer/Counter Register Description” on page 132. Table 58 on page ATmega64( OCnx PORT ...
Page 124
... Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 51. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 2490Q–AVR–06/10 122.) “Timer/Counter Timing Diagrams” on page Figure ATmega64(L) 131. 51. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 124 ...
Page 125
... Compare Matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a Compare Match occurs. 2490Q–AVR–06/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ FPWM ATmega64(L) f clk_I/O ⋅ OCRnA TOP log + 1 ---------------------------------- - log Figure 52 ...
Page 126
... Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2490Q–AVR–06/ ATmega64(L) OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 127
... TCNTn slopes represent Compare Matches between OCRnx and TCNTn. The OCnx inter- rupt flag will be set when a Compare Match occurs. 2490Q–AVR–06/10 f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCRnA is set to zero (0x0000). This feature clk_I TOP log + ---------------------------------- - PCPWM log ATmega64(L) ) Figure 53. The figure 127 ...
Page 128
... Figure 53 f clk_I --------------------------- - OCnxPCPWM ⋅ ⋅ TOP ATmega64(L) OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 illustrates, changing the TOP Table 60 on page 135). ...
Page 129
... PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent Compare Matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a Compare Match occurs. 2490Q–AVR–06/10 54). R PFCPWM Figure 54. The figure shows phase and frequency correct PWM ATmega64( TOP log + 1 = ---------------------------------- - ...
Page 130
... PWM mode. If the OCRnx is set equal to BOTTOM the 2490Q–AVR–06/ shows the output generated is, in contrast to the phase correct mode, symmetrical f OCnxPFCPWM ATmega64(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 131
... OCRnx - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O OCRnx - 1 shows the count sequence close to TOP in various modes. When using phase and ATmega64( therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value OCRnx ...
Page 132
... TOP) OCRnx Old OCRnx Value COM1A1 COM1A0 COM1B1 COM1B0 R/W R/W R/W R COM3A1 COM3A0 COM3B1 COM3B0 R/W R/W R/W R/W ATmega64(L) TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1C1 COM1C0 WGM11 WGM10 R/W R/W R/W R ...
Page 133
... When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). 2490Q–AVR–06/ Table 58 ATmega64( shows the COMnx1:0 bit functionality when 133 ...
Page 134
... COMnA1/COMnB1/COMnC1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 125. shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor- ATmega64(L) (1) when OCRnA/OCRnB/OCRnC for more details. ...
Page 135
... Set OCnA/OCnB/OCnC on Compare Match when up-counting. Clear OCnA/OCnB/OCnC on Compare Match when downcounting special case occurs COMnA1/COMnB1/COMnC1 is set. details. Table 61. Modes of operation supported by the Timer/Counter ATmega64(L) Rn when OCRnA/OCRnB/OC C See “Phase Correct PWM Mode” on page 127. (See “Modes of Operation” on page (1) equals TOP and for more 124 ...
Page 136
... ICES1 – WGM13 R/W R ICNC3 ICES3 – WGM33 R/W R ATmega64(L) Update of TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICRn BOTTOM OCRnA BOTTOM ICRn TOP OCRnA TOP ...
Page 137
... External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B FOC1C – ATmega64( – – – – TCCR1C Figure 137 ...
Page 138
... FOC3B FOC3C – TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R TCNT3[15:8] TCNT3[7:0] R/W R/W R/W R ATmega64( – – – – TCCR3C TCNT1H TCNT1L R/W R/W R/W R TCNT3H TCNT3L R/W ...
Page 139
... OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R OCR3B[15:8] OCR3B[7:0] R/W R/W R/W R OCR3C[15:8] OCR3C[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 115. ATmega64( OCR1AH OCR1AL R/W R/W R/W R OCR1BH OCR1BL R/W R/W R/W R OCR1CH OCR1CL R/W R/W R/W R ...
Page 140
... OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega64( ICR1[7:0] R/W R/W R/W R ...
Page 141
... Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1C flag, located in ETIFR, is set. 2490Q–AVR–06/ – – TICIE3 OCIE3A R R R/W R This register is not available in ATmega103 compatibility mode. ATmega64( OCIE3B TOIE3 OCIE3C OCIE1C ETIMSK R/W R/W R/W R 141 ...
Page 142
... This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections – – ICF3 OCF3A R/W R/W R/W R ATmega64( OCF1B TOV1 OCF0 TOV0 R/W R/W R/W R Table 61 on page 136 ...
Page 143
... Note that a Forced Output Compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C Interrupt Vector is exe- cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. 2490Q–AVR–06/10 ATmega64(L) Table 52 on page 104 for the TOV3 flag 143 ...
Page 144
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O /clk ). The Tn pin is sampled once every system clock cycle by the pin synchroniza /clk clk I/O ATmega64(L) /8, f CLK_I/O CLK_I/O /clk pulse for each positive (CSn2 nega Edge Detector /64, f ...
Page 145
... CS21 CS32 CS22 TIMER/COUNTER3 CLOCK SOURCE clk T3 1. The synchronization logic on the input pins (T3/T2/T1) is shown TSM – – R ATmega64(L) 10-BIT T/C PRESCALER Clear CS10 CS11 CS12 TIMER/COUNTER2 CLOCK SOURCE TIMER/COUNTER1 CLOCK SOURCE clk T2 Figure – ...
Page 146
... Timer/Counter Register Description” on page TCCRn count clear Control Logic direction BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = OCRn ATmega64(L) Figure 61. For the actual place- 2. CPU accessible I/O Registers, including 157. TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCn (Int.Req.) ...
Page 147
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. “Timer/Counter3, Timer/Counter2 and Timer/Counter1 Prescalers” on page ATmega64(L) 144. 147 ...
Page 148
... Signalize that TCNT2 has reached maximum value. Signalize that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 151. ATmega64(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn ( From Prescaler ) top in the following ...
Page 149
... This feature allows OCR2 to be initialized Write to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 2490Q–AVR–06/10 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega64(L) TCNTn OCFn (Int.Req.) OCn 149 ...
Page 150
... Generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis- 2490Q–AVR–06/10 COMn1 Waveform COMn0 Generator FOCn clk I/O ATmega64(L) Figure 64 shows a simplified sche OCn OCn 0 D ...
Page 151
... Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. 2490Q–AVR–06/10 See “8-bit Timer/Counter Register Description” on page 157. Table 65 on page 158. For fast PWM mode, refer to Table 67 on page Figure 155. ATmega64(L) Table 66 on page 159. 68, Figure 69, Figure 70, and Figure 71 Figure 65 ...
Page 152
... PWM outputs. The small horizontal line marks on the TCNT2 slopes represent Compare Matches between OCR2 and TCNT2. 2490Q–AVR–06/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 + Figure 66. The TCNT2 value is in the timing diagram shown as a histo- ATmega64(L) OCn Interrupt Flag Set (COMn1 OC2 clk_I/O ) 152 /2 ...
Page 153
... Table 66 on page f clk_I ----------------- - OCnPWM ⋅ N 256 = f OC2 clk_I/O ATmega64(L) OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 158). The actual OC2 /2 when OCR2 is set to zero. This fea- 153 ...
Page 154
... The PWM frequency for the output when using phase correct PWM can be calculated by the fol- lowing equation: 2490Q–AVR–06/ Table 67 on page f clk_I ----------------- - OCnPCPWM ⋅ N 510 ATmega64(L) Figure 67. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 159). The 154 ...
Page 155
... OCn has a transition from high to low even though there Figure 68 contains timing data for basic Timer/Counter operation. The figure clk I/O clk Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega64(L) Figure 67. When the OCR2 value is MAX the ) is therefore shown MAX BOTTOM BOTTOM + 1 155 ...
Page 156
... I/O clk Tn /8) I/O MAX - 1 TOVn shows the setting of OCF2 in all modes except CTC mode. I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ATmega64(L) /8) clk_I/O MAX BOTTOM OCRn OCRn + 1 OCRn Value BOTTOM + 1 /8) clk_I/O OCRn + 2 156 ...
Page 157
... Pulse Width Modulation (PWM) modes. See page 151. 2490Q–AVR–06/10 /8) I/O Tn /8) I/O TOP - FOC2 WGM20 COM21 COM20 W R/W R/W R ATmega64(L) TOP BOTTOM TOP WGM21 CS22 CS21 CS20 R/W R/W R/W R Table 64 and “Modes of Operation” on BOTTOM + 1 TCCR2 157 ...
Page 158
... A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See for more details. shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct ATmega64(L) (1) Update of TOV2 Flag ...
Page 159
... I External clock source on T2 pin. Clock on falling edge External clock source on T2 pin. Clock on rising edge TCNT2[7:0] R/W R/W R/W R ATmega64(L) (1) “Phase Correct PWM Mode” on page TCNT2 R/W R/W R/W R 159 ...
Page 160
... OCR2[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R ATmega64( OCR2 R/W R/W R/W R TOIE1 OCIE0 TOIE0 TIMSK R/W R/W R/W R TOV1 OCF0 TOV0 TIFR R/W R/W R/W R/W 0 ...
Page 161
... Timer/Counter units and the Port B pin 7 output driver circuit. 2490Q–AVR–06/10 “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” and “8-bit Timer/Counter2 with PWM” on page Timer/Counter1 OC1C Timer/Counter2 OC2 (Figure 72). ATmega64(L) 146. Note that this feature is not Pin OC1C/ OC2/PB7 Figure 73. The schematic 161 ...
Page 162
... D Q OC2 D Q PORTB7 DATA BUS illustrates the modulator in action. In this example the Timer/Counter1 is set to operate clk I/O OC1C OC2 (CTC Mode) PB7 (PORTB7 = 0) PB7 (PORTB7 = 1) 1 (Period) ATmega64(L) Vcc Modulator OC2 / PB7 D Q DDRB7 2 3 Pin OC1C / Figure 162 ...
Page 163
... SPI – Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega64 and peripheral devices or between several AVR devices. The ATmega64 SPI Peripheral includes the following features: Interface • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 164
... For more details on automatic port overrides, refer to 71. (1) Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 74 direction of the user defined SPI pins. ATmega64(L) MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SHIFT ENABLE SCK ...
Page 165
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 9. ATmega64(L) 165 ...
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... SPI_SlaveReceive ; Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 9. ATmega64(L) 166 ...
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... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 2490Q–AVR–06/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATmega64( CPHA SPR1 SPR0 SPCR R/W R/W R 167 ...
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... Sample 1 Setup Table 72. SPR1 SPR0 ATmega64(L) for an example. The CPOL functionality is summa- Trailing Edge Falling Rising and Figure 78 for an example. The CPHA func- Trailing Edge Setup Sample SCK Frequency osc osc f ...
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... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega64 is also used for program memory and EEPROM download- ing or uploading. See SPDR – SPI Data Bit ...
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... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega64(L) Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
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... Double Speed Asynchronous Communication Mode Dual USART The ATmega64 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O Registers as shown in Summary” on page neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility mode, the ATmega64 supports asynchronous operation of USART0 only ...
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... XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 80 2490Q–AVR–06/10 shows a block diagram of the Clock Generation logic. ATmega64(L) Figure 79) if the buffer registers are 172 ...
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... Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and for calculating ATmega64(L) U2X / ...
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... The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency to Table 85 on page 197. Figure 80 for details. depends on the stability of the system clock source therefore recommended to osc ATmega64(L) Equation for Calculating (1) UBRR Value f f OSC OSC UBRRn ...
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... Bits inside brackets are (IDLE Start bit, always low. Data bits (0 to 8). Parity bit. Can be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). An IDLE line must be high. ATmega64(L) Sample Sample FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) 175 ...
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... even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega64(L) ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ...
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... UCSRnC,r16 ret (1) ... USART_Init ( MYUBRR ); ... /* Set baud rate */ UBRRnH = (unsigned char)(ubrr>>8); UBRRnL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); 1. See “About Code Examples” on page 9. ATmega64(L) 177 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega64(L) 178 ...
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... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega64(L) 179 ...
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... The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo- Transmitter ing and pending transmissions are completed, that is, when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD pin. 2490Q–AVR–06/10 ATmega64(L) 180 ...
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... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “About Code Examples” on page 9. ATmega64(L) 181 ...
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... Get status and ninth bit, then data */ /* from buffer */ status = UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the ninth bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 9. ATmega64(L) 182 ...
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... The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 2490Q–AVR–06/10 “Parity Bit Calculation” on page 176 ATmega64(L) and “Parity Checker” on page 183. 183 ...
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... UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 9. IDLE ATmega64(L) START Figure 83 BIT ...
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... STOP Figure 85. For Double Speed mode the first low level must be delayed to (B). ATmega64( Figure 85 shows the sampling of the (A) (B) (C) 10 0/1 0/1 0/1 6 0/1 185 ...
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... D S ⋅ – for Double Speed mode the ratio of the fastest incoming data rate that can be fast and Table 76 list the maximum Receiver baud rate error that can be tolerated. Note ATmega64( ----------------------------------- fast ( ) ...
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... D R (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega64(L) Max Total Recommended Max Error (%) Receiver Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Max Total Recommended Max Error (%) Receiver Error (%) +5.66/-5.88 ±2.5 +4.92/-5.08 ±2.0 +4.35/-4.48 ±1.5 +3.90/-4.00 ±1.5 +3.53/-3.61 ±1.5 +3.23/-3.30 ±1.0 187 ...
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... Data written to UDRn when the UDREn flag is not set, will be ignored by the USART transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will 2490Q–AVR–06/ RXB[7:0] TXB[7:0] R/W R/W R/W R/W R ATmega64( UDnR (Read) UDnR (Write) R/W R/W R 188 ...
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... Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. 2490Q–AVR–06/ RXCn TXCn UDREn FEn DORn R R ATmega64( UPEn U2Xn MPCMn UCSRnA R R R/W R 189 ...
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... The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRC sets the number of data bits (Character Size frame the Receiver and Transmitter use. 2490Q–AVR–06/10 “Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega64(L) 187 TXENn UCSZn2 RXB8n TXB8n UCSRnB R/W R 190 ...
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... This register is not available in ATmega103 compatibility mode. UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity ATmega64( USBSn UCSZn1 UCSZn0 UCPOLn R/W R/W R/W R UCSRnC 191 ...
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... UCSZn1 UCSZn0 Transmitted Data Changed (Output of TxD Pin) Rising XCK Edge Falling XCK Edge ATmega64(L) Stop Bit(s) 1-bit 2-bit Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) ...
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... R/W R/W R/W R UBRRH is not available in mega103 compatibility mode 186). The error values are calculated using the following BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ ATmega64( UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R Table 82 ⎞ Closest Match • ...
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... UBRRn Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% 8 -3.5% 7 0.0% 6 -7.0% 5 0.0% 3 8.5% 3 0.0% 2 8.5% 2 0.0% 1 8.5% 1 0.0% 1 -18.6% 1 -25.0% 0 8.5% 0 0.0% – – – – – – – – 125 Kbps 115.2 Kbps ATmega64( 2.0000 MHz osc U2X = 1 U2X = 0 UBRRn Error UBRRn Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7.0% 7 0.0% 3 8.5% 5 0.0% 2 8.5% 3 0.0% 1 8.5% 2 0.0% 1 -18. ...
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... Kbps 0.5 Mbps ATmega64( 7.3728 MHz osc U2X = 0 U2X = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0.0% 63 0.2% 23 0.0% 47 2.1% 15 0.0% 31 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0. ...
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... Kbps 1.3824 Mbps ATmega64( 14.7456 MHz osc U2X = 0 U2X = 1 Error UBRRn Error UBRRn 0.0% 383 0.0% 767 0.0% 191 0.0% 383 0.0% 95 0.0% 191 0.0% 63 0.0% 127 0.0% 47 0.0% 95 0.0% 31 0.0% 63 0.0% 23 0.0% 47 0.0% 15 0.0% 31 0.0% 11 0.0% 23 0.0% 7 0.0% 15 ...
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... Mbps 2.304 Mbps ATmega64( 20.0000 MHz osc U2X = 0 U2X = 1 Error UBRRn Error UBRRn 0.0% 520 0.0% 1041 0.0% 259 0.2% 520 0.0% 129 0.2% 259 0.0% 86 -0.2% 173 0.0% 64 0.2% 129 0.0% 42 0.9% 86 0.0% 32 -1.4% 64 0.0% 21 -1.4% 42 0.0% 15 1.7% 32 ...
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... Device 2 SDA SCL Description The device that initiates and terminates a transmission. The Master also generates the SCL clock. The device addressed by a Master. The device placing data on the bus. The device reading data from the bus. ATmega64( ........ Device 198 ...
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... As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. 2490Q–AVR–06/10 Figure 86, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega64(L) 328. Two Data Stable 199 ...
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... All addresses of the format 1111 xxx should be reserved for future purposes. Figure 89. Address Packet Format 2490Q–AVR–06/10 START STOP START Addr MSB SDA SCL 1 START ATmega64(L) REPEATED START Addr LSB R STOP ACK 9 200 ...