ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 83

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Alternate Functions of
Port F
2490Q–AVR–06/10
Table 41. Overriding Signals for Alternate Functions in PE3..PE0
The Port F has an alternate function as analog input for the ADC as shown in
Port F pins are configured as outputs, it is essential that these do not switch when a conversion
is in progress. This might corrupt the result of the conversion. In ATmega103 compatibility mode
Port F is input only. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI),
PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
Table 42. Port F Pins Alternate Functions
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PE3/AIN1/OC3A
0
0
0
0
OC3B ENABLE
OC3B
0
0
0
AIN1 INPUT
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test Clock)
ADC3 (ADC input channel 3)
ADC2 (ADC input channel 2)
ADC1 (ADC input channel 1)
ADC0 (ADC input channel 0)
PE2/AIN0/XCK0
0
0
0
0
UMSEL0
XCK0 OUTPUT
0
0
XCK0 INPUT
AIN0 INPUT
.
.
PE1/PDO/TXD0
TXEN0
0
TXEN0
1
TXEN0
TXD0
0
0
–
–
PE0/PDI/RXD0
RXEN0
PORTE0 • PUD
0
0
0
0
RXD0
–
RXEN0
0
ATmega64(L)
Table
42. If some
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