ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 107

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Asynchronous
Operation of the
Timer/Counter
ASSR – Asynchronous
Status Register
Asynchronous
Operation of
Timer/Counter0
2490Q–AVR–06/10
• Bit 3 – AS0: Asynchronous Timer/Counter0
When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk
written to one, Timer/Counter 0 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and
TCCR0 might be corrupted.
• Bit 2 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
• Bit 1 – OCR0UB: Output Compare Register0 Update Busy
When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set.
When OCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.
• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy
When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set.
When TCCR0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0,
the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary stor-
age register is read.
When Timer/Counter0 operates asynchronously, some considerations must be taken.
•
Bit
0x30 (0x50)
Read/Write
Initial Value
Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter0, the timer registers TCNT0, OCR0, and TCCR0 might be corrupted. A safe
procedure for switching clock source is:
1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.
2. Select clock source by setting AS0 as appropriate.
3. Write new values to TCNT0, OCR0, and TCCR0.
4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.
5. Clear the Timer/Counter0 interrupt flags.
6. Enable interrupts, if needed.
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
AS0
R/W
3
0
TCN0UB
2
R
0
OCR0UB
R
1
0
TCR0UB
ATmega64(L)
R
0
0
I/O
ASSR
. When AS0 is
107