ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 29

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Pull-up and Bus
Keeper
Timing
2490Q–AVR–06/10
Figure 12. External SRAM Connected to the AVR
The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port Register to zero before entering sleep.
The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper can be
disabled and enabled in software as described in
B” on page
the AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External memory devices have different timing requirements. To meet these requirements, the
ATmega64 XMEM interface provides four different wait states as shown in
tant to consider the timing specification of the external memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement of the ATmega64. The access time for the external memory is defined to
be the time from receiving the chip select/address until the data of this address actually is driven
on the bus. The access time cannot exceed the time from the ALE pulse is asserted low until
data must be stable during a read sequence (t
page
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to
ure
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Conse-
quently the XMEM interface is not suited for synchronous operation.
162, and
337). The different wait states are set up in software. As an additional feature, it is possible
34. When enabled, the Bus Keeper will ensure a defined logic level (zero or one) on
Table 137
AVR
AD7:0
A15:8
ALE
to
WR
RD
Table
144.
D
G
LLRL
“XMCRB – External Memory Control Register
+ t
Q
RLRH
- t
DVRH
in
D[7:0]
A[15:8]
A[7:0]
RD
WR
Table 137
SRAM
ATmega64(L)
Table
Figure 159
to
Table 144 on
4. It is impor-
to
Fig-
29