ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 22

• Manufacturer Part Number: ATmega64
• Manufacturer: Atmel Corporation

Specifications of ATmega64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

EEARH and EEARL –
EEPROM Address
Register
EEDR – EEPROM Data
Register
EECR – EEPROM
Control Register
2490Q–AVR–06/10
• Bits 15..11 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bits 10..0 – EEAR10..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 2
Kbytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 2,048.
The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit
0x1F (0x3F)
0x1E (0x3E)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
R/W
R/W
14
R
X
R
–
6
0
6
0
6
–
0
EEAR5
R/W
R/W
13
R
R
–
5
0
X
5
0
5
–
0
EEAR4
R/W
R/W
12
R
R
–
4
0
X
4
0
4
–
0
EEAR3
EERIE
R/W
R/W
R/W
11
R
X
–
3
0
3
0
3
0
EEAR10
EEMWE
EEAR2
R/W
R/W
R/W
R/W
10
2
0
X
X
2
0
2
EEAR1
EEAR9
EEWE
R/W
R/W
R/W
R/W
1
0
X
X
X
1
9
1
ATmega64(L)
EEAR8
EEAR0
EERE
LSB
R/W
R/W
R/W
R/W
0
0
X
X
0
0
8
0
EEARH
EEARL
EEDR
EECR
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