AT91SAM7SE512B-AUR Atmel, AT91SAM7SE512B-AUR Datasheet - Page 557
AT91SAM7SE512B-AUR
Manufacturer Part Number
AT91SAM7SE512B-AUR
Description
IC ARM7 MUC FLASH 512K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE512B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE512
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE512B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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38.3
38.3.1
38.3.2
38.3.3
6222F–ATARM–14-Jan-11
Product Dependencies
I/O Lines
Power Management
Interrupt
For further details on the USB Device hardware implementation, see the specific Product Prop-
erties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals
DDP and DDM are available from the product boundary.
DDP and DDM are not controlled by any PIO controllers. The embedded USB physical trans-
ceiver is controlled by the USB device peripheral.
To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to
assign this I/O in input PIO mode.
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL
with an accuracy of ± 0.25%.
Thus, the USB device receives two clocks from the Power Management Controller (PMC): the
master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to inter-
face with the bus USB signals (recovered 12 MHz domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be
enabled before any read/write operations to the UDP registers including the UDP_TXVC
register.
The USB device interface has an interrupt line connected to the Interrupt Controller.
Handling the USB device interrupt requires programming the Interrupt Controller before config-
uring the UDP.
SAM7SE512/256/32 Preliminary
557
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