AT91SAM7SE512B-CUR Atmel, AT91SAM7SE512B-CUR Datasheet - Page 655
AT91SAM7SE512B-CUR
Manufacturer Part Number
AT91SAM7SE512B-CUR
Description
IC ARM7 MUC FLASH 512K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE512B-CUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE512
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE512B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
Quantity
Price
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43.2.5
43.2.5.1
43.2.6
43.2.6.1
43.2.6.2
43.2.6.3
6222F–ATARM–14-Jan-11
SDRAM Controller (SDRAMC)
Serial Peripheral Interface (SPI)
SPI: Baudrate Set to 1
SPI: Bad Serial Clock Generation on 2nd Chip Select
SDRAMC: PDC Buffer in 16-bit SDRAM while the Core Accesses SDRAM
SPI: Software Reset Must Be Written Twice
The software must handle RTT event as interrupt and should not poll RTT_SR.
When the SAM7SE interfaces with 16-bit SDRAM memory and the processor accesses the
SDRAM, either for instruction fetch or data read/write, the data transferred by the PDC from
SDRAM buffers to the peripherals might be corrupted. Transfers from peripherals to SDRAM
buffers are not affected.
Map the transmit PDC buffers in internal SRAM or Flash.
When the Baudrate is set at 1 (so, the serial clock frequency equals the master clock), and when
the BITS field (number of bits to be transmitted) in SPI_CSRx equals an odd value (in this case
9, 11, 13 or 15), an additional pulse will be generated on SPCK.
It does not occur when the BITS field is equal to 8, 10, 12, 14 or 16 and the Baudrate is equal
to 1.
None.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM7SE512/256/32 Preliminary
655
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