MC9S08SH8CWJR Freescale Semiconductor, MC9S08SH8CWJR Datasheet - Page 215
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MC9S08SH8CWJR
Manufacturer Part Number
MC9S08SH8CWJR
Description
IC MCU 8BIT 8K FLASH 20WSOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH8CWJR.pdf
(338 pages)
Specifications of MC9S08SH8CWJR
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Interface Type
SPI, SCI, RS-232
Maximum Clock Frequency
5 MHz, 40 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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1
14.2.7
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
14.3
The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote
devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.
The transmitter and receiver operate independently, although they use the same baud rate generator. During
normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The following describes each of the blocks of the SCI.
14.3.1
As shown in
Freescale Semiconductor
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
Reset
TXINV
Field
ORIE
NEIE
FEIE
PEIE
4
3
2
1
0
W
R
1
Functional Description
SCI Data Register (SCIxD)
Baud Rate Generation
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
0 Transmit data not inverted
1 Transmit data inverted
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
R7
T7
Figure
0
7
14-12, the clock source for the SCI baud rate generator is the bus-rate clock.
R6
T6
0
6
Table 14-7. SCIxC3 Field Descriptions (continued)
Figure 14-11. SCI Data Register (SCIxD)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
R5
T5
0
5
R4
T4
0
4
Description
Chapter 14 Serial Communications Interface (S08SCIV4)
R3
T3
3
0
R2
T2
0
2
R1
T1
0
1
R0
T0
0
0
215
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