MC9S08SH8CWJR Freescale Semiconductor, MC9S08SH8CWJR Datasheet - Page 54
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MC9S08SH8CWJR
Manufacturer Part Number
MC9S08SH8CWJR
Description
IC MCU 8BIT 8K FLASH 20WSOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH8CWJR.pdf
(338 pages)
Specifications of MC9S08SH8CWJR
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Interface Type
SPI, SCI, RS-232
Maximum Clock Frequency
5 MHz, 40 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 4 Memory
control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory.
Refer to
refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or
header file normally is used to translate these names into the appropriate absolute addresses.
4.7.1
Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
Table 4-7
54
Reset
PRDIV8
DIVLD
Field
DIV
5:0
7
6
W
R
Table 4-3
shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
DIVLD
FLASH Clock Divider Register (FCDIV)
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erase
timing pulses are one cycle of this internal FLASH clock which corresponds to a range of 5 μs to 6.7 μs. The
automated programming logic uses an integer number of these pulses to complete an erase or program
operation. See
0
7
and
= Unimplemented or Reserved
Table 4-4
PRDIV8
Equation 4-1
0
6
if PRDIV8 = 1 — f
Figure 4-5. FLASH Clock Divider Register (FCDIV)
if PRDIV8 = 0 — f
Table 4-6. FCDIV Register Field Descriptions
for the absolute address assignments for all FLASH registers. This section
MC9S08SH8 MCU Series Data Sheet, Rev. 3
and
0
5
Equation
FCLK
FCLK
4-2.
= f
0
4
= f
Bus
Description
Bus
÷ (8 × (DIV + 1))
÷ (DIV + 1)
3
0
DIV
0
2
Freescale Semiconductor
0
1
Eqn. 4-1
Eqn. 4-2
0
0
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