PK20N512VLQ100 Freescale Semiconductor, PK20N512VLQ100 Datasheet - Page 36
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PK20N512VLQ100
Manufacturer Part Number
PK20N512VLQ100
Description
IC ARM CORTEX MCU 512K 144-LQFP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheet
1.PK20X128VLQ100.pdf
(74 pages)
Specifications of PK20N512VLQ100
Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LVD, POR, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PK20N512VLQ100
Manufacturer:
FSL
Quantity:
55
Company:
Part Number:
PK20N512VLQ100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
36
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP1a
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 22. EzPort switching specifications
EP3
Figure 10. EzPort Timing Diagram
EP5
EP6
EP4
EP7
Preliminary
EP8
EP9
EP2
2 x t
Min.
2.7
—
—
EZP_CK
—
—
5
5
2
5
0
Freescale Semiconductor, Inc.
f
f
Max.
SYS
SYS
3.6
12
12
—
—
—
—
—
—
/2
/8
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V