PK30N512VLQ100 Freescale Semiconductor, PK30N512VLQ100 Datasheet - Page 19

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PK30N512VLQ100

Manufacturer Part Number
PK30N512VLQ100
Description
IC ARM CORTEX MCU 512K 144-LQFP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheet

Specifications of PK30N512VLQ100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
102
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 37x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
PK30N512VLQ100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
4. 15pF load
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Freescale Semiconductor, Inc.
FB_CLK
Symbol
Symbol
f
Symbol
FLASH
T
T
J
A
FlexBus clock
Flash clock
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
Description
Die junction temperature
Ambient temperature
Description
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
2
C signals.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 9. Thermal operating requirements
Preliminary
TBD
Min.
Min.
100
1.5
16
2
Min.
–40
–40
Max.
Max.
12
36
32
36
2
1
Max.
Bus clock
Bus clock
125
105
cycles
cycles
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
Notes
Notes
Unit
°C
°C
General
1
2
3
4
2
19

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