WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 26

• Manufacturer Part Number: WJLXT972MLC.A4-864115
• Description: TXRX ETH 10/100 SGL PORT 48-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1044

LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
Figure 5
Cortina Systems
When the LXT972M PHY is first powered on, reset, or encounters a link failure state, it
checks the MDIO register configuration bits to determine the line speed and operating
conditions to use for the network link.
Figure 5
set by the Hardware Control or MDIO interface.
Initialization Sequence
®
•
•
•
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Section 5.4.2, Reduced-Power Modes
Section 5.4.3, Reset
Section 5.4.4, Hardware Configuration Settings
shows the LXT972M PHY initialization sequence. The configuration bits may be
Reset MDIO Registers to
Initialize MDIO Registers
Control Interface at last
Pass Control to MDIO
values read at H/W
Power-up or Reset
Hardware Reset or
Read H/W Control
Power-Up Reset
Interface
Interface
Software
Reset?
Yes
B3502-02
5.4 Initialization
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