WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 33

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WJLXT972MLC.A4-864115

Manufacturer Part Number
WJLXT972MLC.A4-864115
Description
TXRX ETH 10/100 SGL PORT 48-LQFP
Manufacturer
Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
1008-1044

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Part Number
Manufacturer
Quantity
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Part Number:
WJLXT972MLC.A4-864115
Manufacturer:
Cortina Systems Inc
Quantity:
10 000
LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
5.6.4
.
Table 15
5.6.5
5.6.6
5.6.7
Cortina Systems
100 Mbps
10 Mbps
1. Test Loopback is enabled when register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
Table 15
collision signals. Carrier sense is not generated when a packet is transmitted and in full-
duplex mode.
Carrier Sense, Loopback, and Collision Conditions
Error Signals
When the LXT972M PHY is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
The TX_ER function that forces ‘H’ symbols out on the TPOP/TPON twisted pair is not
implemented in the LXT972M PHY.
Collision
The LXT972M PHY asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
Table 15
collision signals.
Loopback
The LXT972M PHY provides the following loopback functions:
Figure 10
information on loopback functions, see
Conditions, on page
®
Speed
• CRS is always generated when the LXT972M PHY receives a packet from the line.
• CRS is also generated when the LXT972M PHY is in half-duplex mode when a packet
LXT972M Single-Port 10/100 Mbps PHY Transceiver
is transmitted.
Section 5.6.7.1, Operational Loopback
Section 5.6.7.2, Internal Digital Loopback (Test Loopback)
summarizes the conditions for assertion of carrier sense, data loopback, and
summarizes the conditions for assertion of carrier sense, data loopback, and
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex,
register bit 16.8 = 0
Half-Duplex,
register bit 16.8 = 1
Duplex Condition
shows LXT972M PHY operational and test loopback paths. For more
33.)
Receive Only
Transmit or Receive
Receive Only
Transmit or Receive
Transmit or Receive
Carrier Sense
Table 15, Carrier Sense, Loopback, and Collision
Loop-
back
Test
Yes
Yes
Yes
No
No
1, 2
Section 5.6.7, Loopback, on page
Operational
back
Loop-
Yes
No
No
No
No
1, 2
None
Transmit and Receive
None
Transmit and Receive
Transmit and Receive
5.6 MII Operation
Collision
Page 33
33.

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