ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet - Page 77
ELLXT971ABE.A4-870479
Manufacturer Part Number
ELLXT971ABE.A4-870479
Description
TXRX FAST ETH EXT TEMP 64-PBGA
Manufacturer
Cortina Systems Inc
Specifications of ELLXT971ABE.A4-870479
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
1008-1004
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LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 44
Cortina Systems
RESET_L Pulse Width and Recovery Timing
®
RESET_L pulse width
RESET_L recovery
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
LXT971A Single-Port 10/100 Mbps PHY Transceiver
testing.
performance. The PHY comes out of reset after a delay of no more than 300 μ s. System designers should
consider this value as a minimum value. After de-asserting RESET_L, the MAC should delay no less than
300 μ s before accessing the MDIO port.
Parameter
delay2
Symbol
t1
t2
Min
10
–
Typ
–
1
Max
300
–
Units
7.2 AC Timing Diagrams and
ns
μ s
Test Conditions
–
–
Parameters
Page 77