DS90UR908QSQE/NOPB National Semiconductor, DS90UR908QSQE/NOPB Datasheet - Page 21

• Manufacturer Part Number: DS90UR908QSQE/NOPB
• Description: IC DESERIALIZER 65MHZ 48LLP
• Manufacturer: National Semiconductor

Specifications of DS90UR908QSQE/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90UR908QSQE/NOPBTR

Serial Bus Control — Optional
The DS90UR908Q may also be configured by the use of a
serial control bus that is I2C protocol compatible. By default,
the I2C reg_0x00'h is set to 00'h and all configuration is set
by control/strap pins. A write of 01'h to reg_0x00'h will enable/
allow configuration by registers; this will override the control/
strap pins. Multiple devices may share the serial control bus
since multiple addresses are supported. See
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Out-
put signal. Both SCL and SDA signals require an external pull
up resistor to V
sistor to V
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
The third pin is the ID[X] pin. This pin sets one of five possible
device addresses. Two different connections are possible.
The pin may be pulled to V
kΩ resistor. Or a 10 kΩ pull up resistor (to V
V
to set other three possible addresses may be used. See
7
The Serial Bus protocol is controlled by START, START-Re-
peated, and STOP phases. A START occurs when SCL
transitions Low while SDA is High. A STOP occurs when SDA
transition High while SCL is also HIGH. See
To communicate with a remote device, the host controller
(master) sends the slave address and listens for a response
from the slave. This response is referred to as an acknowl-
edge bit (ACK). If a slave on the bus is addressed correctly,
it Acknowledges (ACKs) the master by driving the SDA bus
low. If the address doesn't match a device's slave address, it
Not-acknowledges (NACKs) the master by letting SDA be
pulled High. ACKs also occur on the bus when data is being
transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the mas-
ter is reading data, the master ACKs after every data byte is
DDIO
for the Des. Do not tie ID[x] directly to ground.
)) and a pull down resistor of the recommended value
DDIO
DDIO
may be used. The resistor value may be
. For most applications a 4.7 k pull up re-
DD
(1.8V, NOT V
FIGURE 21. START and STOP Conditions
Figure 21
DDIO
Figure
DD
)) with a 10
1.8V, NOT
20.
Table
21
received to let the slave know it wants to receive another data
byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a stop condition on the bus. All
communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus
ends with a Stop condition. A READ is shown in
and a WRITE is shown in
If the Serial Bus is not required, the three pins may be left
open (NC).
Resistor
RID kΩ
(5%tol)
Open
0.47
2.7
8.2
FIGURE 20. Serial Control Bus Connection
TABLE 7. ID[x] Resistor Value
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
Address
7'b
Figure
23.
30105151
8b' 1110 1100 (h'EC)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
0 appended
Address
(WRITE)
8'b
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Figure 22
30105141