DS90UB901QSQE/NOPB National Semiconductor, DS90UB901QSQE/NOPB Datasheet - Page 7
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DS90UB901QSQE/NOPB
Manufacturer Part Number
DS90UB901QSQE/NOPB
Description
IC SER/DESER 10-43MHZ 16B 32-LLP
Manufacturer
National Semiconductor
Datasheet
1.DS90UB902QSQXNOPB.pdf
(44 pages)
Specifications of DS90UB901QSQE/NOPB
Function
Serializer
Data Rate
688Mbps
Input Type
LVCMOS
Output Type
CML
Number Of Inputs
1
Number Of Outputs
1
Voltage - Supply
1.71 V ~ 1.89 V, 3 V ~ 3.6 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
32-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS90UB901QSQE/NOPBTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PASS
FPD-LINK III INTERFACE
RIN+
RIN-
POWER AND GROUND
VDDSSCG
VDDIO1/2/3
VDDD
VDDR
VDDCML
VDDPLL
VSS
Pin Name
25, 16, 8
Pin No.
DAP
31
35
36
13
30
34
38
4
Power, Analog Rx Analog Power, 1.8V ±5%
Power, Analog Bidirectional Channel Driver Power, 1.8V ±5%
Power, Analog PLL Power, 1.8V ±5%
Power, Digital
Power, Digital
Power, Digital
Ground, DAP
Input/Output,
Input/Output,
I/O, Type
LVCOMS
Output,
CML
CML
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Noninverting differential input, bidirectional control channel output. The
interconnect must be AC Coupled with a 100 nF capacitor.
Inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
LVTTL I/O Buffer Power, The single-ended outputs and control input are powered
from V
Digital Core Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
DDIO
. V
DDIO
7
can be connected to a 1.8V ±5% or 3.3V ±10%
Description
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