NCN6001DTBR2G ON Semiconductor, NCN6001DTBR2G Datasheet - Page 12

• Manufacturer Part Number: NCN6001DTBR2G
• Description: IC INTERFACE SMART CARD 20TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCN6001DTBR2G

• Applications: Smart Card
• Interface: Microcontroller
• Voltage - Supply: 2.75 V ~ 5.5 V
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6001DTBR2GOS; NCN6001DTBR2GOS; NCN6001DTBR2GOSTR

11. Chip Bank 1 = Asynchronous cards, four slots addresses 1 to 4.
12. Address 101 and bits [b0 : b4] not documented in the table are reserved for future use.
a NCN6001 silicon standpoint, care must be observed to
avoid uncontrolled operation of the interface sharing the
same digital bus. When this code is presented on the digital
bus, the CRD_RST signal of any interface sharing the CS
signal, immediately reflects the digital content of the MOSI
bit b4 register. Similarly, the MISO register of the shared
interface is presented on the SPI port. Consequently, data
collision, at MISO level, and uncontrolled card operation are
Table 2. WRT_REG Bits Definitions and Functions
Although using the %111XXXXX code is harmless from
Chip Bank 2 = Asynchronous or synchronous card, single slot.
Address 111 is reserved for future use.
BANK
CHIP
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
ADDRESS
b7
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
b6
X
X
X
X
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
b5
X
X
X
X
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
RST
RST
RST
RST
RST
RST
RST
RST
RST
b4
0
0
0
0
0
0
−
0
0
0
0
0
0
−
PARAMETERS
CLK
b3
0
0
1
1
0
0
0
0
0
0
−
0
0
1
1
0
0
0
0
0
0
−
I/O
b2
0
1
0
1
0
0
0
0
1
1
−
0
1
0
1
0
0
0
0
1
1
−
http://onsemi.com
C4
b1
0
0
1
1
0
0
1
1
0
0
−
0
0
1
1
0
0
1
1
0
0
−
12
C8
b0
0
1
0
1
0
1
0
1
0
1
−
0
1
0
1
0
1
0
1
0
1
−
likely to happen if the system uses a common Chip Select
line. It is strongly recommended to run a dedicated CS bit to
any external circuit intended to use the $111xxxxx code.
Low when the internal register of the chip is programmed to
accommodate different hardware conditions (NO/NC,
Special/Normal, SLO_SLP/FST_SLP). Generally speaking,
such a configuration shall take place during the Power On
Reset to avoid CRD_RST activation.
On the other hand, the CRD_RST signal will be forced to
CRD_CLK
MOSI bits
[b3:b2]
Low
Low
1/1
1/2
1/4
1/1
1/2
1/4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
CRD_VCC
MOSI bits
[b1:b0]
1.8 V
3.0 V
5.0 V
1.8 V
3.0 V
5.0 V
0
−
−
−
−
−
−
−
0
−
−
−
−
−
−
−
−
Data to Sync. Card
CRD_DET
MOSI bits
SLO_SLP
SLO_SLP
FST_SLP
FST_SLP
Special
Normal
Special
Normal
[b7:b0]
RFU
RFU
NO
NC
NO
NC
−
−
−
−
−
−
−
−