AD6620AS Analog Devices Inc, AD6620AS Datasheet - Page 33

• Manufacturer Part Number: AD6620AS
• Description: IC DGTL RCVR SIGNAL PROC 80-PQFP
• Manufacturer: Analog Devices Inc

Specifications of AD6620AS

• Rohs Status: RoHS non-compliant
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: *
• Applications: -

Mode = 0
If MODE is low during the access, the interface is in Mode 0.
In Mode 0 the CS, RD and the WR lines control the access
type. While an access is being performed, or if the serial port
D[7:0]
A[2:0]
D[7:0]
A[2:0]
CLK
RDY
RDY
WR
RD
CS
CLK
WR
RD
CS
NOTES:
1
2
3
3
2
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
1
2
3
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.
2
1
2
1
t
SAM
t
NOTES:
1
2
3
ZR
THE NEXT WRITE MAY BE INITIATED ON CLK, N.
RDY IS DRIVEN LOW ASYNCHRONOUSLY BY WR AND CS GOING LOW AND RETURNS HIGH ON THE
RISING EDGE OF CLK "N+2".
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE.
t
t
SAM
SAM
t
RDY
N
t
SC
t
SC
t
RDYL
N
N+1
DATA VALID
ADDRESS VALID
N+1
ADDRESS VALID
t
N+2
DD
is accessing the chip, the RDY line goes low at the start of
the access. When the internal cycle is complete the RDY line
is released.
t
N+2
t
RDYH
HC
t
t
HM
HA
DATA VALID
N+3
t
HC
t
SC
t
RDY
t
N+3
t
HC
ZD
t
N+4
HC
t
HA
N
N
AD6620