TSL208R TAOS, TSL208R Datasheet - Page 2

• Manufacturer Part Number: TSL208R
• Description: Photodiodes Linear Array 200 DPI
• Manufacturer: TAOS
• Type: Linear Sensor Arrayr

Specifications of TSL208R

• Peak Wavelength: 1000 nm
• Maximum Rise Time: 500 ns
• Maximum Fall Time: 500 ns
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Photodiode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSL208R
512 y 1 LINEAR SENSOR ARRAY
TAOS031E − MAY 2007
Terminal Functions
Detailed Description
2
Copyright E 2007, TAOS Inc.
AO
CLK
GND
SI
SO
VDD
NAME
TERMINAL
†
The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)
is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 513
and the output assumes a high-impedance state. Note that this 513
output of the 512
as early as the 514
The voltage developed at analog output (AO) is given by:
where:
AO is driven by a source follower with an internal 330-Ω pulldown resistor (no external resistor is required). The
output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When
the device is not in the output phase, AO is in a high impedance state.
A 0.1 μF bypass capacitor should be connected between V
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
V
V
R
E
t
NO.
1, 7
int
out
drk
e
e
4
3
5
2
6
I/O
I/O
O
O
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm
is the incident irradiance in μW/cm
is integration time in seconds
I
I
I
I
th
Analog output.
Clock. The clock controls the charge transfer, pixel output and reset.
Ground (substrate). All voltages are referenced to the substrate.
Serial input. SI defines the start of the data out sequence.
Serial output. SO signals the end of the data out sequence.
Supply voltage for both analog and digital circuits.
pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
th
clock pulse, thereby initiating another pixel output cycle.
V
out
= V
r
drk
+ (R
www.taosinc.com
th
e
2
clock rising edge, the SI pulse is clocked out of the shift register
) (E
e
) (t
int
)
DESCRIPTION
DESCRIPTION
DD
and ground as close as possible to the device.
th
clock pulse is required to terminate the
r
2
The LUMENOLOGY r Company
)
†
. As the SI pulse