PI6C20800SAE Pericom Semiconductor, PI6C20800SAE Datasheet

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PI6C20800SAE

Manufacturer Part Number
PI6C20800SAE
Description
Clock Buffer Clock Buffer 3.3V/5V 160MHz
Manufacturer
Pericom Semiconductor
Datasheet

Specifications of PI6C20800SAE

Supply Voltage (max)
3.465 V
Maximum Operating Temperature
70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
• Phase jitter filter for PCIe
• Eight Pairs of Differential Clocks
• Low skew < 50ps (PI6C20800S), <60ps (PI6C20800SI)
• Low Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Industrial Temperature Option - PI6C20800SI
• Packaging (Pb-Free & Green):
— 48-Pin TSSOP (A)
Block Diagram
PLL/BYPASS#
— 48-Pin SSOP (V)
SRC_STOP#
SRC#
PWRDWN#
SRC_DIV#
SRC
PLL_BW#
10-0150
OE_INV
OE [0:7]
SCLK
SDA
PLL
Controller
SMBus
Output
Control
®
application
DIV
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
OUT3
OUT3#
OUT4
OUT4#
OUT5
OUT5#
OUT6
OUT6#
OUT7
OUT7#
LOCK
1
Description
PI6C20800S is a PCI Express
clock buffer designed to be a companion to PI6C410BS PCI
Express clock generator for Intel server chipsets. The device
distributes the differential SRC clock from PI6C410BS to eight
differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is
LOW. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is LOW, the output
clocks are Tristated. When PWRDWN# is LOW, the SDA and
SCLK inputs must be Tristated.
Pin Configuration
PLL/BYPASS#
SRC_DIV#
OUT0#
OUT1#
OUT2#
OUT3#
SRC#
OUT0
OUT1
OUT2
OUT3
SCLK
OE_0
OE_3
OE_1
OE_2
SRC
SDA
VSS
V
V
V
V
V
DD
DD
DD
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
®
, high-speed, low-noise differential
HCSL Clock Buffer
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI Express
V
V
I
LOCK
OE_7
OE_4
OUT7
OUT7#
OE_INV
V
OUT6
OUT6#
OE_6
OE_5
OUT5
OUT5#
V
V
OUT4
OUT4#
PLL_BW#
SRC_STOP#
PWRDWN#
V
PI6C20800S
REF
DD_A
SS_A
DD
SS
DD
SS
PS8887D
®
03/29/10
1:8

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PI6C20800SAE Summary of contents

Page 1

Features • Phase jitter filter for PCIe application ® • Eight Pairs of Differential Clocks • Low skew < 50ps (PI6C20800S), <60ps (PI6C20800SI) • Low Cycle-to-cycle jitter < 50ps • Output Enable for all outputs • Outputs Tristate control via SMBus • Power Management Control • Programmable PLL Bandwidth • PLL or Fanout operation • 3.3V Operation • Industrial Temperature Option - PI6C20800SI • Packaging (Pb-Free & Green): — 48-Pin SSOP (V) — 48-Pin TSSOP (A) Block Diagram OE_INV OE [0:7] Output SRC_STOP# Control PWRDWN# SCLK SMBus ...

Page 2

Pin Descriptions Pin Name Type SRC_DIV# Input SRC & SRC# Input OE [0:7] Input OE_INV Input OUT[0:7] & OUT[0:7]# Output PLL/BYPASS# Input SCLK Input SDA I/O I Input REF SRC_STOP# Input PLL_BW# Input PWRDWN# Input LOCK Output V Power DD V Ground SS V Ground ...

Page 3

Data Read Protocol 1 bit 7 bits bits Start Slave Register W Ack bit Addr offset Note: 2. Register offset for indicating the starting register for indexed block write and indexed block read. Data Byte 0: Control Register Bit Descriptions SRC_DIV Divide Normal PLL/BYPASS Fanout 1 = PLL PLL Bandwidth HIGH Bandwidth LOW Bandwidth 3 ...

Page 4

Data Byte 2: Control Register Bit Descriptions Allow control of OUTPUTS with 3 assertion of SRC_STOP Free running Stopped with SRC_Stop Data Byte 3: Control Register Bit Descriptions RESERVED Data Byte 4: Pericom ID ...

Page 5

Functionality PWRDWN# OUT 1 Normal 0 I × Float REF Power Down (PWRDWN# assertion) PWRDWN# OUT OUT# Power Down (PWRDWN# De-assertion) PWRDWN# OUT OUT# 10-0150 OUT# SRC_Stop# Normal 1 LOW 0 Figure 1. Power down sequence Tstable <1ms Tdrive_PwrDwn# <300us, >200mV ...

Page 6

Current-mode output buffer characteristics of OUT[0:7], OUT[0:7 (3.3V ± 5 Iout V = 0.85V max OUT Figure 9. Simplified diagram of current-mode output buffer Differential Clock Buffer characteristics Symbol OUT ...

Page 7

Absolute Maximum Ratings Symbol V 3.3V Core Supply Voltage DD_A V 3.3V I/O Supply Voltage DD V Input HIGH Voltage IH V Input LOW Voltage IL Ts Storage Temperature V ESD Protection ESD Note: 1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. DC Electrical Characteristics Symbol Parameters V 3.3V Core Supply Voltage DD_A V 3.3V I/O Supply Voltage DD V 3.3V Input HIGH Voltage IH ...

Page 8

AC Switching Characteristics Symbol Parameters SRC/SRC# Input Frequency PLL Mode F in SRC/SRC# Input Frequency Bypass Mode Rise and Fall Time (measured between 0.175V to 0.525V) rise fall ΔT / rise Rise and Fall Time Variation ΔT fall T Input to Output Propagation Delay pd Output-to-Output Skew (PI6C20800S) T skew Output-to-Output Skew (PI6C20800SI) V Voltage HIGH (Measured at 100MHz @ 3.3V) HIGH V Max. Voltage OVS V Min. Voltage UDS V Voltage LOW LOW ...

Page 9

... Nom. 0-8˚ .008 0.20 .0135 0.34 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com DESCRIPTION: 48-Pin, 300-Mil Wide, SSOP PACKAGE CODE PI6C20800S PCI Express 1:8 ® HCSL Clock Buffer DOCUMENT CONTROL NO. ...

Page 10

... Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. (1,2) Ordering Information Ordering Code PI6C20800SVE PI6C20800SAE PI6C20800SIVE PI6C20800SIAE Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • ...

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