IES5501D Hendon Semiconductors, IES5501D Datasheet - Page 2

• Manufacturer Part Number: IES5501D
• Description: Buffers & Line Drivers 2.7-5.5V 4.3mA 90ns 400-1000kHz
• Manufacturer: Hendon Semiconductors

Specifications of IES5501D

• Logic Family: IE5501
• Number Of Channels Per Chip: Dual
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 4.3 mA
• Logic Type: Bidirectional Bus Buffer
• Package / Case: MSOP-8L
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5
5.1
6
6.1
The power supply voltage for the IES5501 may be any
voltage in the range 2.7 V to 5.5 V. The threshold level
below which the output will begin to match the input is 33%
of V
with the required bus voltage, switching threshold, and
noise margins, in mind.
6.2
The two buffers (S
The buffers can be driven from either direction, with the
same response. When port 1 of the buffer is being driven
low (<0.33V
driven low by the IC to provide the buffered output.
The “input” side is determined by the lowest externally
driven signal. Therefore if port 1 is externally pulled to
V
V
that it becomes V
subsequently become lower than port 1 by the amount of
the offset voltage (V
external device pulling it low, control of the buffering
operation will switch, and port 2 will become the “input”.
The voltage at port 1 will then become V
V
(less than an offset voltage) the external devices are
effectively in control.
2008 Jun 13, Revision 1.4
Sx1
Sx2
OFFSET
CC
PINNING INFORMATION
FUNCTIONAL DESCRIPTION
= 500 mV, the buffer will pull port 2 down further such
= 250 mV, and port 2 is externally pulled to
. Hence, the operating voltage should be chosen
Pinning layout
V
S
. When both ports are being held almost equal
CC
A1
Fig.2 Pinning diagram (SO8 / MSOP8)
GND
, S
, GND - DC supply pins
S
S
EN
CC
A1
A2
A2
) by another device on the bus, port 2 will be
, S
1
2
3
4
Sx2
A
B1
and S
Sx2
, S
= V
B2
+ V
IES5501
Sx1
B
- Buffer inputs/outputs
) are identical and symmetrical.
OFFSET
+ V
OFFSET
< V
Sx1
. Should port 2
8
7
6
5
pin5501-8
Sx1
) by means of an
V
S
S
n.c.
CC
B1
B2
= V
Sx2
+
2
Fast Dual Bi-Directional Bus Buffer
5.2
* Recommended I
compatibility.
6.3
The Enable input is used to disable the buffer, for the
purpose of isolating sections of the bus. The IC should only
be disabled when the bus is idle. This prevents truncation
of commands which may confuse other devices on the
bus.
Enable may also be used to progressively activate
sections of the bus during system start-up. Bus sections
slow to respond on power-up can be kept isolated from the
main system to avoid interference and collisions.
The Enable pin may be pulled up higher than the Vcc of the
buffer, further enhancing the capability of the IES5501 in a
level shifting role. For example, a microprocessor could
drive Enable, S
and S
Similarly, the threshold level of the Enable pin allows a
1.8V device to disable an IES5501 with a V
The Enable pin includes an internal 2µA pull-down current
which will act to disable the device, should the pin be left
floating.
EN
S
S
GND
n.c.
S
S
V
SYMBOL
A1
A2
B2
B1
CC
B2
Pin description
Enable - Activate Buffer Operations
ports are at 3.3V.
1
2
3
4
5
6
7
8
A1
PIN
and S
2
C bus orientation for device family
B1
Enable
Buffer A, Port 1 (SCL
Buffer A, Port 2 (SCL
Supply Ground
not connected
Buffer B, Port 2 (SDA
Buffer B, Port 1 (SDA
Positive supply
at 5V, while the buffer V
DESCRIPTION
Product Specification
IES5501
CC
OUT
IN
IN
OUT
of 3.3V.
)*
)*
)*
)*
CC
, S
A2