MAX5978ETJ+ Maxim Integrated Products, MAX5978ETJ+ Datasheet - Page 26
![Hot Swap & Power Distribution 0-16V HOTSWAP CONTLR W/10BIT CUR VOLT MON](/photos/16/13/161373/tqfn32_sml.jpg)
MAX5978ETJ+
Manufacturer Part Number
MAX5978ETJ+
Description
Hot Swap & Power Distribution 0-16V HOTSWAP CONTLR W/10BIT CUR VOLT MON
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX5978ETJ.pdf
(38 pages)
Specifications of MAX5978ETJ+
Product
Controllers & Switches
Supply Voltage (max)
16 V
Supply Voltage (min)
0 V
Power Dissipation
2759 mW
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Supply Current
2.5 mA
Package / Case
TQFN-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
0 to 16V, Hot-Swap Controller with 10-Bit
Current, Voltage Monitor, and 4 LED Drivers
All voltage-measurement values are compared with the
contents of minimum- and maximum-value registers,
and if the most recent measurement exceeds the stored
maximum or is less than the stored minimum, the corre-
sponding register is updated with the new value. These
Table 31. ADC Minimum Voltage Conversion Register Format (High-Order Bits)
Table 32. ADC Minimum Voltage-Conversion Register Format (Low-Order Bits)
Table 33. ADC Maximum Voltage-Conversion Register Format (High-Order Bits)
Table 34. ADC Maximum Voltage-Conversion Register Format (Low-Order Bits)
26
Description:
Register Title:
Register Addresses:
Description:
Register Title:
Register Addresses:
Description:
Register Title:
Register Addresses:
Description:
Register Title:
Register Addresses:
vmax_9
vmin_9
Minimum and Maximum Value Detection
Bit 7
Bit 7
Bit 7
Bit 7
—
—
R
R
R
R
for Voltage-Measurement Values
vmax_8
vmin_8
Bit 6
Bit 6
Bit 6
Bit 6
—
—
R
R
R
R
Minimum voltage conversion result, high-order bits [9:2]
min_mon_msb
0x0C
Minimum voltage-conversion result, low-order bits [1:0]
min_mon_lsb
0x0D
Maximum voltage-conversion result, high-order bits [9:2]
max_mon_msb
0x0E
Maximum voltage-conversion result, low-order bits [1:0]
max_mon_lsb
0x0F
vmax_7
vmin_7
Bit 5
Bit 5
Bit 5
Bit 5
—
—
R
R
R
R
vmax_6
vmin_6
Bit 4
Bit 4
Bit 4
Bit 4
—
R
—
R
R
R
vmax_5
vmin_5
Bit 3
Bit 3
Bit 3
Bit 3
—
R
—
R
R
R
peak-detection registers are read accessible through the
I
registers are reset to 0xFF, and the maximum-value reg-
isters are reset to 0x00. These reset values are loaded
upon startup or at any time as commanded by register
peak_log_rst (see Table 35).
2
C interface (see Tables 31 to 34). The minimum-value
vmax_4
vmin_4
Bit 2
Bit 2
Bit 2
Bit 2
—
R
—
R
R
R
vmax_3
vmax_1
vmin_1
vmin_3
Bit 1
Bit 1
Bit 1
Bit 1
R
R
R
R
vmax_2
vmax_0
vmin_2
vmin_0
Bit 0
Bit 0
Bit 0
Bit 0
R
R
R
R
VALUE
RESET
VALUE
RESET
VALUE
RESET
RESET
VALUE
0x00
0xFF
0x03
0x00
—
—
—
—