LC4064ZE-5TN100C Lattice, LC4064ZE-5TN100C Datasheet - Page 17

• Manufacturer Part Number: LC4064ZE-5TN100C
• Description: CPLD - Complex Programmable Logic Devices 64MC 64 I/O Ultra Low Power 1.8V
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064ZE-5TN100C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 277.78 MHz
• Delay Time: 5.8 ns
• Number Of Programmable I/os: 64
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.08 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Programmable Type: CPLD
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 5.8ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000ZE Family Data Sheet
mated test equipment. This equipment can then be used to program ispMACH 4000ZE devices during the testing
of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
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device, stored in E
CMOS memory. The ispMACH 4000ZE device contains 32 UES bits that can be configured by
the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the ispMACH 4000ZE devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The ispMACH 4000ZE devices are well-suited for applications that require hot socketing capability. Hot socketing a
device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The isp-
MACH 4000ZE devices provide this capability for input voltages in the range 0V to 3.0V.
Density Migration
The ispMACH 4000ZE family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
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