LC4064ZE-5TN100C Lattice, LC4064ZE-5TN100C Datasheet - Page 25
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LC4064ZE-5TN100C
Manufacturer Part Number
LC4064ZE-5TN100C
Description
CPLD - Complex Programmable Logic Devices 64MC 64 I/O Ultra Low Power 1.8V
Manufacturer
Lattice
Series
ispMACH®r
Datasheet
1.LC4064ZE-5TN100C.pdf
(60 pages)
Specifications of LC4064ZE-5TN100C
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
277.78 MHz
Delay Time
5.8 ns
Number Of Programmable I/os
64
Operating Supply Voltage
1.8 V
Supply Current
0.08 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
1.9 V
Supply Voltage (min)
1.7 V
Programmable Type
CPLD
Voltage - Input
1.7 V ~ 1.9 V
Speed
5.8ns
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4064ZE-5TN100C
Manufacturer:
Lattice
Quantity:
25
Company:
Part Number:
LC4064ZE-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LC4064ZE-5TN100C-7I
Manufacturer:
LATTICE
Quantity:
5
Part Number:
LC4064ZE-5TN100CA1L
Manufacturer:
LATTCE
Quantity:
20 000
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Lattice Semiconductor
t
Control Delays
t
t
t
t
t
t
t
Internal Oscillator
t
t
t
t
t
t
t
t
t
t
t
t
Optional Delay Adjusters
t
t
t
t
LVTTL_in
LVCMOS15_in
LVCMOS18_in
LVCMOS25_in
LVCMOS33_in
PCI_in
t
LVTTL_out
SRR
BCLK
PTCLK
BSR
PTSR
BIE
PTOE
GPTOE
OSCSU
OSCH
OSCEN
OSCOD
OSCNOM
OSCvar
TMRCO20
TMRCO10
TMRCO7
TMRRSTO
TMRRR
TMRRSTPW
INDIO
EXP
BLA
IOI
IOO
Parameter
Input Buffer Delays
Output Buffer Delays
Asynchronous Reset or Set Recovery Delay
GLB PT Clock Delay
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Power Guard Block Input Enable Delay
Macrocell PT OE Delay
Global PT OE Delay
Oscillator DYNOSCDIS Setup Time
Oscillator DYNOSCDIS Hold Time
Oscillator OSCOUT Enable Time (To Stable)
Oscillator Output Delay
Oscillator OSCOUT Nominal Frequency
Oscillator Variation of Nominal Frequency
Oscillator TIMEROUT Clock (Negative Edge) to Out
(20-Bit Divider)
Oscillator TIMEROUT Clock (Negative Edge) to Out
(10-Bit Divider)
Oscillator TIMEROUT Clock (Negative Edge) to Out
(7-Bit Divider)
Oscillator TIMEROUT Reset to Out (Going Low)
Oscillator TIMEROUT Asynchronous Reset Recovery
Delay
Oscillator TIMEROUT Reset Minimum Pulse Width
Input Register Delay
Product Term Expander Delay
Additional Block Loading Adders
Using LVTTL Standard with
Hysteresis
Using LVCMOS 1.5 Standard
Using LVCMOS 1.8 Standard
Using LVCMOS 2.5 Standard with
Hysteresis
Using LVCMOS 3.3 Standard with
Hysteresis
Using PCI Compatible Input with
Hysteresis
Output Configured as TTL Buffer
Over Recommended Operating Conditions
Description
t
t
t
t
t
t
t
t
t
t
INREG
MCELL
ROUTE
IN
IN
IN
IN
IN
IN
EN
Base Parameter
, t
, t
, t
, t
, t
, t
, t
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
GCLK_IN
DIS
25
, t
BUF
, t
, t
, t
, t
, t
, t
GOE
GOE
GOE
GOE
GOE
GOE
ispMACH 4000ZE Family Data Sheet
Min.
5.00
5.00
3.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LC4032ZE
-4
12.50
Max.
1.20
1.40
1.10
1.20
1.60
2.30
1.80
5.00
4.00
5.00
7.50
6.00
5.00
4.00
1.00
0.40
0.04
0.60
0.20
0.00
0.80
0.80
0.80
0.20
2.00
30
—
—
—
Min.
5.00
5.00
3.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LC4064ZE
-4
12.50
Max.
1.70
1.30
1.50
1.85
1.90
1.70
3.15
2.15
5.00
4.00
5.00
7.50
6.00
5.00
4.00
1.00
0.40
0.05
0.60
0.20
0.00
0.80
0.80
0.80
0.20
30
—
—
—
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%