LCMXO640C-5TN144C Lattice, LCMXO640C-5TN144C Datasheet - Page 16

• Manufacturer Part Number: LCMXO640C-5TN144C
• Description: CPLD - Complex Programmable Logic Devices 640 LUTS 113 I/O
• Manufacturer: Lattice

Specifications of LCMXO640C-5TN144C

• Memory Type: SRAM
• Number Of Macrocells: 320
• Maximum Operating Frequency: 600 MHz
• Delay Time: 4.9 ns
• Number Of Programmable I/os: 256
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-13. Memory Core Reset
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
PIO Groups
On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells
and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO
groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective
sysIO buffers and PADs.
On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O
pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-14. Group of Four Programmable I/O Cells
GSRN
RSTA
RSTB
Four PIOs
Programmable Disable
Memory Core
This structure is used on the
left and right of MachXO devices
2-13
PIO B
PIO A
PIO C
PIO D
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
PADB "C"
PADA "T"
PADC "T"
PADD "C"
MachXO Family Data Sheet
Port A[17:0]
Port B[17:0]
Architecture