LCMXO640C-L-EV Lattice, LCMXO640C-L-EV Datasheet
LCMXO640C-L-EV
Specifications of LCMXO640C-L-EV
Related parts for LCMXO640C-L-EV
LCMXO640C-L-EV Summary of contents
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MachXO™ Standard Evaluation Board - Revisions 001 & 002 User’s Guide March 2008 Revision: EB21_01.6 ...
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... MachXO core is selectable. The core voltage is changed by moving a single current sense resistor. Once a correct set of supply voltages has been applied to the MachXO, the device can be programmed. The MachXO can be programmed and verified with a Lattice JTAG download cable, which should be connected to the 1x10 SIP header on the board (1149.1 JTAG interface). The ispVM and verifi ...
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... Lattice Semiconductor logo. For example, the DIP oscillator is on the southwest corner of the board, and the Lattice logo is on the northeast corner of the board. ...
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... Lattice Semiconductor Figure 1. MachXO Standard Evaluation Board JTAG Programming Interface RJ-45 Connector Area SMA Connector Area ispClock5610 DIP Oscillator Power Supply The MachXO Standard Evaluation Board includes two locations to apply power. On the east side of the board are a pair of banana jacks (JP28 and JP29) and a coaxial DC connector (JP30), which receive power from either a bench power supply or a brick style power supply ...
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... Lattice Semiconductor Adjacent to JP25-27 are current sense resistors. These permit the measurement of the current flowing from each of the power supplies. A single resistor can be moved to permit 1.2V, 3.3V Table 2. MachXO Core Voltage Selection The remaining current sense resistors permit the measurement of the V Table 3 ...
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... Lattice Semiconductor The default configuration for jumper JP6 is to configure the TDI from JP7 to be routed to the MachXO first. The TDO from the MachXO is routed to the ispClock device. TDO from the ispClock is connected to the JTAG header JP7. However Figure 3 shows the board can be configured to only have the MachXO accessible by the JTAG header. It can also be confi ...
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... Lattice Semiconductor board. There are also locations to insert connectors and resistors. These connections are useful for performing I/O characterization. The silk screen markings on the evaluation board are designed to make it easy to locate resources on the board and related connections to the MachXO. • Parts are numbered in a consistent fashion. Each part starts at reference designator ‘1’ in the northwest corner of the board (i.e. R1, C1, U1, L1… ...
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... Lattice Semiconductor Figure 4. Prototype Grid 1 and 2 Resistor Pad Configuration The resistor pads are 0603 surface mount form factor. The 0603 resistor in the center has a short-circuit trace between the resistor pads. This permits the signal to be driven to the prototype area without the addition of a SMT zero ohm resistor series resistor with a non-zero value is needed, this short-circuit trace can be removed. The pull-up resistors within this grid can be confi ...
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... Lattice Semiconductor Figure 5. Prototype Grid 4 Short-circuit Prototype Grid 5 : The last of the prototype grid is designed for use with an LCD display. U3 can be populated by a Lumex LCD-S501C39TR five-element, seven-segement LCD display. When this display is populated mounted on the rows between U3 and JP23/JP24. JP23 and JP24 can then be populated with general-purpose headers. ...
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... Oscillator and Clock Inputs The MachXO Standard Evaluation Board provides the ability to supply selectable reference frequencies to the MachXO device. The board provides a unique clock source distribution method. A Lattice ispClock5610 is included on the board to provide a number of different clock frequencies to the MachXO device. The ispClock5610 receives a reference clock from one of two sources on the board. The primary clock source for the ispClock5610 is the on-board DIP oscillator ...
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... Lattice Semiconductor Figure 6. Oscillator Positions Full-size to ispClock JP9 Pin 1 Note: XU2 pin 9 is routed to one of the two PLLs included on larger MachXO devices. These MachXO PLLs are not available on the MachXO640 device. XU2 pin 9 provides input to the PLL_T input pin M5. JP2 and JP3 are routed to the second set of PLL input pins on the MachXO device. On the MachXO640, these input pins are general purpose I/O ...
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... Lattice Semiconductor See the ispClock5610 Family Data Sheet and the Lattice PAC-Designer gramming the ispClock. More information and software downloads can be found on the Lattice web site at www.lat- ticesemi.com/ispclock. ispClock Configuration The ispClock5610 has multiple configuration pins. The evaluation board includes a number of headers on the board allowing these confi ...
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... Date June 2006 September2006 February 2007 March 2007 April 2007 June 2007 March 2008 Ordering Part Number LCMXO2280C-L-EV LCMXO640C-L-EV Version 01.0 Initial release. 01.1 Updated schematic in Appendix A. 01.2 Updated Switch Assignments table. Updated ispClock Configuration section. 01.3 Added Ordering Information section. ...
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... Lattice Semiconductor Appendix A. PCB Schematic Figure 8. MachXO Control and Programming Interfaces MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 14 ...
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... Lattice Semiconductor Figure 9. MachXO I/O Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide PT5B/PT6F/PT9B/CLK0 D7 PT5A/PT6E/PT9A D8 15 PB5D/PB6F/PB9B P8 PB5C/PB6E/PB9A P7 ...
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... Lattice Semiconductor Figure 10. Power Section PGND Vin 16 SGND MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide ...
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... Lattice Semiconductor Figure 11. Miscellaneous Interfaces MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide GND_4 43 GND_3 42 GND_2 41 GND_1 40 GND_0 ...
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... Lattice Semiconductor Figure 12. ispClock5610 Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 1 1 ROUTING ROUTING AND AND DIVIDERS DIVIDERS OUTPUT OUTPUT GNDD_4 17 GNDD_3 16 GNDD_2 15 GNDD_1 48 GNDD_0 23 GNDA 14 VCCA 13 TEST2 45 VCCD_1 33 TEST1 46 VCCD_0 24 1 VCC 14 GND 7 18 ...
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... Lattice Semiconductor Figure 13. LED and LCD Connections MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide LIN36 LIN35 LIN37 LIN34 LIN38 23 18 LIN33 LIN28 LIN32 DP4 LIN29 LIN27 LIN30 LIN26 LIN31 LIN25 LIN20 LIN24 DP3 LIN21 LIN19 LIN22 LIN18 ...
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... Lattice Semiconductor Figure 14. Miscellaneous MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 20 ...
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... Lattice Semiconductor Figure 15. Prototype Area MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 21 ...
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... Lattice Semiconductor Figure 16. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 22 ...
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... Lattice Semiconductor Figure 17. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 23 ...
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... Lattice Semiconductor Figure 18. Prototype Area (Cont.) MachXO Standard Evaluation Board Revisions 001 & 002 User’s Guide 24 ...