AGLP125V5-CSG289 Actel, AGLP125V5-CSG289 Datasheet - Page 71
![FPGA - Field Programmable Gate Array 125K System Gates](/photos/16/14/161498/landingpageactel-2_sml.jpg)
AGLP125V5-CSG289
Manufacturer Part Number
AGLP125V5-CSG289
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet
1.AGLP125V5-CSG289.pdf
(128 pages)
Specifications of AGLP125V5-CSG289
Processor Series
AGLP125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
4
Data Ram Size
4608 bit
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
CSP-289
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Global Resource Characteristics
Figure 2-21 • Example of Global Tree Use in an AGLP125 Device for Clock Routing
CCC
AGLP125 Clock Tree Topology
Clock delays are device-specific.
global tree presented in
It is used to drive all D-flip-flops in the device.
Figure 2-21
Figure 2-21
is driven by a CCC located on the west side of the AGLP125 device.
R ev i si o n 1 1
is an example of a global tree used for clock routing. The
IGLOO PLUS Low Power Flash FPGAs
Central
Global Rib
VersaTile
Rows
Global Spine
2- 57
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