SMAX-624CG-ACTEL Actel, SMAX-624CG-ACTEL Datasheet

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SMAX-624CG-ACTEL

Manufacturer Part Number
SMAX-624CG-ACTEL
Description
Programming Socket Adapters & Emulators SILICON SCULPTOR ADAPTER MODULE
Manufacturer
Actel

Specifications of SMAX-624CG-ACTEL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SX Family FPGAs
Leading Edge Performance
Specifications
SX Product Profile
June 2006
© 2006 Actel Corporation
Device
Capacity
Logic Modules
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
Typical Gates
System Gates
Combinatorial Cells
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Setup
0.25 ns Clock Skew
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1,080 Flip-Flops
0.35 µ CMOS
Std, –1, –2, –3
A54SX08
144, 176
12,000
C, I, M
3.7 ns
0.8 ns
8,000
768
512
256
130
208
100
144
Yes
84
3
Features
Std, –1, –2, –3
A54SX16
16,000
24,000
C, I, M
3.9 ns
0.5 ns
1,452
66 MHz PCI
CPLD and FPGA Integration
Single-Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
924
528
175
208
100
176
Yes
3
See the Actel website for the latest version of the datasheet.
Std, –1, –2, –3
A54SX16P
144, 176
16,000
24,000
C, I, M
4.4 ns
0.5 ns
1,452
924
528
175
208
100
Yes
Yes
3
Std, –1, –2, –3
A54SX32
144, 176
313, 329
32,000
48,000
C, I, M
4.6 ns
0.1 ns
2,880
1,800
1,080
249
208
Yes
3
v3.2
u
e
i

Related parts for SMAX-624CG-ACTEL

SMAX-624CG-ACTEL Summary of contents

Page 1

... Std, –1, –2, –3 Std, –1, –2, – – 208 208 100 100 144, 176 176 – – 144 – See the Actel website for the latest version of the datasheet. v3.2 ™ A54SX16P A54SX32 16,000 32,000 24,000 48,000 1,452 2,880 924 1,800 528 ...

Page 2

... A54SX16P – A54SX32 – Note: Package Definitions (Consult your local Actel sales representative for product availability): PLCC = Plastic Leaded Chip Carrier PQFP = Plastic Quad Flat Pack TQFP = Thin Quad Flat Pack VQFP = Very Thin Quad Flat Pack PBGA = Plastic Ball Grid Array FBGA = Fine Pitch (1 ...

Page 3

Table of Contents SX Family FPGAs General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

...

Page 5

... The SX family architecture is described as a “sea-of- modules” architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. The Actel SX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). v3.2 ...

Page 6

SX Family FPGAs The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional Routing Tracks ...

Page 7

... Module Organization Actel has arranged all C-cell and R-cell logic modules into horizontal banks called clusters. There are two types of clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells ...

Page 8

SX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 of ...

Page 9

... SX device. Other Architectural Features Technology The Actel SX family is implemented on a high-voltage twin-well CMOS process using 0.35 µ design rules. The metal-to-metal antifuse is made combination of amorphous silicon and dielectric material with barrier metals and has a programmed (" ...

Page 10

... SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow diagram website) for more information. Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven integrated static timing analyzer and constraints editor. ...

Page 11

... PRB The procedure for programming an SX device using Silicon Sculptor II are as follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready production, Actel offers device through distribution programming from the factory. For more details on programming SX devices, refer to the ...

Page 12

SX Family FPGAs Table 1-4 • Recommended Operating Conditions Parameter Temperature Range* 3.3 V Power Supply Tolerance 5.0 V Power Supply Tolerance Note: *Ambient temperature ( used for commercial and industrial; case temperature (T A Table 1-5 • ...

Page 13

PCI Compliance for the SX Family The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-6 • A54SX16P DC Specifications (5.0 V PCI Operation) Symbol Parameter V ...

Page 14

SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Table 1-7 • A54SX16P AC Specifications for (PCI Operation) Symbol Parameter I Switching Current High OH(AC) (Test Point) I Switching Current High OL(AC) (Test Point) I Low Clamp Current CL slew ...

Page 15

Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 PCI I Mininum OH –0.10 –0.15 –0.20 ...

Page 16

SX Family FPGAs A54SX16P DC Specifications (3.3 V PCI Operation) Table 1-8 • A54SX16P DC Specifications (3.3 V PCI Operation) Symbol Parameter V Supply Voltage for Array CCA V Supply Voltage required for Internal Biasing CCR V Supply Voltage for ...

Page 17

A54SX16P AC Specifications (3.3 V PCI Operation) Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Switching Current High 0 < V 0.3V I OH(AC) 0.7V (Test Point) V Switching Current High V 0.6V I OL(AC) ...

Page 18

SX Family FPGAs Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0. –0.05 PCI I Minimum ...

Page 19

Power-Up Sequencing Table 1-10 • Power-Up Sequencing V V CCA CCR A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 5.0 V 3.3 V 5.0 V Note: No inputs should be driven (high or low) ...

Page 20

SX Family FPGAs Evaluating Power in SX Devices A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package ...

Page 21

Table 1-13 shows capacitance devices. Table 1-13 • Capacitance Values for Devices A54SX08 A54SX16 C (pF) 4.0 4.0 EQM C (pF) 3.4 3.4 EQI C (pF) 4.7 4.7 EQO C (pF) 1.6 1.6 EQCR C 0.615 0.615 EQHV C 60 ...

Page 22

SX Family FPGAs Step 1: Define Terms Used in Formula Module Number of logic modules switching at f (Used 50%) m Average logic modules switching rate f (MHz) (Guidelines: f/10) m Module capacitance C (pF) EQM Input Buffer Number of ...

Page 23

Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1200 1000 800 600 400 200 Figure 1-11 • Power Dissipation Junction Temperature (T ) ...

Page 24

SX Family FPGAs Table 1-15 • Package Thermal Characteristics Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic ...

Page 25

SX Timing Model Input Delays I/O Module t = 1.5 ns INY t = 0.5 ns SUD Routed Clock t = 1.5 ns (100% Load) RCKH F = 250 MHz MAX Hardwired Clock t = ...

Page 26

SX Family FPGAs GND 50% 50 Out 1 DLH DHL Figure 1-13 • Output Buffer Delays Load 1 (used to measure propagation delay) To Output Under Test 35 pF Figure ...

Page 27

Register Cell Timing Characteristics D t SUD CLK Q CLR PRESET Figure 1-17 • Flip-Flops Timing Characteristics Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input characteristics are common to all SX family members. ...

Page 28

SX Family FPGAs A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...

Page 29

Table 1-17 • A54SX08 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...

Page 30

SX Family FPGAs A54SX16 Timing Characteristics Table 1-18 • A54SX16 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...

Page 31

Table 1-18 • A54SX16 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...

Page 32

SX Family FPGAs A54SX16P Timing Characteristics Table 1-19 • A54SX16P Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect DC ...

Page 33

Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) HCKL t Minimum ...

Page 34

SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description TTL/PCI Output Module Timing t Data-to-Pad LOW to HIGH DLH t Data-to-Pad HIGH to LOW DHL t Enable-to-Pad ENZL t Enable-to-Pad, ...

Page 35

A54SX32 Timing Characteristics Table 1-20 • A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, V Parameter Description 1 C-Cell Propagation Delays t Internal Array Module PD 2 Predicted Routing Delays Routing Delay, Direct Connect ...

Page 36

SX Family FPGAs Table 1-20 • A54SX32 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, V Parameter Description Dedicated (Hardwired) Array Clock Network t Input LOW to HIGH (pad to R-Cell input) HCKH t Input HIGH to LOW (pad to R-Cell input) ...

Page 37

Pin Description CLKA/B Clock A and B These pins are 3 5.0 V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set ...

Page 38

...

Page 39

... Package Pin Assignments 84-Pin PLCC Figure 2-1 • 84-Pin PLCC (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 84-Pin PLCC v3.2 54SX Family FPGAs 2-1 ...

Page 40

Family FPGAs 84-Pin PLCC A54SX08 Pin Number Function 1 V CCR 2 GND 3 V CCA 4 PRA, I/O 5 I CCI 8 I/O 9 I/O 10 I/O 11 TCK, I/O 12 TDI, I/O 13 ...

Page 41

... PQFP 208 1 Figure 2-2 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 208-Pin PQFP v3.2 54SX Family FPGAs 2-3 ...

Page 42

Family FPGAs 208-Pin PQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I I/O 5 I/O I I/O 7 I/O I/O 8 I/O I/O 9 I/O ...

Page 43

PQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 73 NC I/O 74 I/O I I/O 76 PRB, I/O PRB, I/O 77 GND GND CCA 79 GND GND CCR 81 I/O I/O ...

Page 44

Family FPGAs 208-Pin PQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 145 V V CCA CCA 146 GND GND 147 I/O I/O 148 V V CCI 149 I/O I/O 150 I/O I/O 151 I/O I/O 152 I/O I/O 153 ...

Page 45

... TQFP 144 1 Figure 2-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 144-Pin TQFP v3.2 54SX Family FPGAs 2-7 ...

Page 46

Family FPGAs 144-Pin TQFP A54SX08 A54SX16P Pin Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 TMS TMS ...

Page 47

TQFP A54SX08 A54SX16P Pin Number Function Function 73 GND GND 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 I/O I CCA CCA CCI CCI 81 GND GND 82 ...

Page 48

... Family FPGAs 176-Pin TQFP 176 1 Figure 2-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 176-Pin TQFP v3.2 ...

Page 49

TQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 1 GND GND 2 TDI, I/O TDI, I I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 TMS ...

Page 50

Family FPGAs 176-Pin TQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 69 HCLK HCLK 70 I/O I/O 71 I/O I/O 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I/O 77 I/O I/O 78 ...

Page 51

TQFP A54SX16, A54SX08 A54SX16P Pin Number Function Function 137 I/O I/O 138 I/O I/O 139 I/O I/O 140 V V CCI CCI 141 I/O I/O 142 I/O I/O 143 I/O I/O 144 I/O I/O 145 I/O I/O 146 I/O ...

Page 52

... Family FPGAs 100-Pin VQFP 100 1 Figure 2-5 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html 100-Pin VQFP v3.2 ...

Page 53

VQFP A54SX16, Pin A54SX08 A54SX16P Number Function Function 1 GND GND 2 TDI, I/O TDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 TMS TMS CCI CCI 9 GND GND ...

Page 54

... Family FPGAs 313-Pin PBGA Figure 2-6 • 313-Pin PBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html v3 ...

Page 55

PBGA 313-Pin PBGA Pin A54SX32 Pin Number Function Number A1 GND AC5 A3 NC AC7 A5 I/O AC9 A7 I/O AC11 A9 I/O AC13 A11 I/O AC15 A13 V AC17 CCR A15 I/O AC19 A17 I/O AC21 A19 I/O ...

Page 56

Family FPGAs 313-Pin PBGA Pin A54SX32 Number Function Number H20 I/O H22 V CCI H24 I/O J1 I/O J3 I I/O J11 I/O J13 CLKA J15 I/O J17 I/O J19 I/O J21 GND J23 ...

Page 57

... PBGA Figure 2-7 • 329-Pin PBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html v3.2 54SX Family FPGAs 2-19 ...

Page 58

Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number A1 GND AA13 A2 GND AA14 A3 V AA15 CCI A4 NC AA16 A5 I/O AA17 A6 I/O AA18 A7 V AA19 CCI A8 NC AA20 A9 I/O AA21 A10 ...

Page 59

PBGA 329-Pin PBGA Pin A54SX32 Pin Number Function Number D3 I/O F22 D4 TCK, I/O F23 I/O G20 D10 I/O G21 D11 V G22 CCA D12 ...

Page 60

Family FPGAs 329-Pin PBGA Pin A54SX32 Number Function Number T22 I/O T23 I/O U1 I CCA U4 I/O U20 I/O U21 V CCA U22 I/O U23 I CCI V2 I/O V3 I/O 2 ...

Page 61

... FBGA Figure 2-8 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html v3.2 54SX Family FPGAs 2-23 ...

Page 62

Family FPGAs 144-Pin FBGA Pin A54SX08 Number Function Number A1 I/O A2 I/O A3 I CCA A6 GND A7 CLKA A8 I/O A9 I/O A10 I/O A11 I/O A12 I/O B1 I/O B2 GND B3 ...

Page 63

Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v3.2) v3.1 The "Ordering Information" (June 2003) The Product Plan was removed since ...

Page 64

... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0) 1276 401 450 Fax 650 ...

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