SMAX-624CG-ACTEL Actel, SMAX-624CG-ACTEL Datasheet - Page 37

• Manufacturer Part Number: SMAX-624CG-ACTEL
• Description: Programming Socket Adapters & Emulators SILICON SCULPTOR ADAPTER MODULE
• Manufacturer: Actel

Specifications of SMAX-624CG-ACTEL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
CLKA/B
These pins are 3.3 V / 5.0 V PCI/TTL clock inputs for clock
distribution networks. The clock input is buffered prior
to clocking the R-cells. If not used, this pin must be set
LOW or HIGH on the board. It must not be left floating.
(For A54SX72A, these clocks can be configured as
bidirectional.)
GND
LOW supply voltage.
HCLK
This pin is the 3.3 V / 5.0 V PCI/TTL clock input for sequential
modules. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or
HIGH on the board. It must not be left floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, 3.3 V PCI or 5.0 V PCI specifications. Unused
I/O pins are automatically tristated by the Designer Series
software.
NC
This pin is not connected to circuitry within the device.
PRA, I/O
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality.
PRB, I/O
The Probe B pin is used to output data from any node
within the device. This diagnostic pin can be used in
conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device.
The Probe B pin can be used as a user-defined I/O when
verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
Clock A and B
Ground
Dedicated (hardwired) Array Clock
Input/Output
No Connection
Probe A
Probe B
v3.2
TCK
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to
page
boundary scan state machine reaches the "logic reset"
state.
TDI
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to
functions as an I/O when the boundary scan state
machine reaches the "logic reset" state.
TDO
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-2 on page
the boundary scan state machine reaches the “logic
reset” state.
TMS
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI, and TDO pins
are boundary scan pins (refer to
Once the boundary scan pins are in test mode, they will
remain in that mode until the internal boundary scan
state machine reaches the "logic reset" state. At this
point, the boundary scan pins will be released and will
function as regular I/O pins. The "logic reset" state is
reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the
IEEE 1149.1 specifications.
V
Supply voltage for I/Os. See
V
Supply voltage for Array. See
V
Supply voltage for input tolerance (required for internal
biasing). See
CCI
CCA
CCR
1-6). This pin functions as an I/O when the
Table 1-1 on page
Test Clock
Test Data Input
Test Data Output
Test Mode Select
Supply Voltage
Supply Voltage
Supply Voltage
1-6). This pin functions as an I/O when
Table 1-2 on page
Table 1-1 on page
Table 1-1 on page
1-5.
Table 1-2 on page
SX Family FPGAs
1-6). This pin
Table 1-2 on
1-5.
1-5.
1-6).
1-33