LFXP3C-3QN208C Lattice, LFXP3C-3QN208C Datasheet - Page 19
![FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O](/photos/16/15/161504/qfp208_sml.jpg)
LFXP3C-3QN208C
Manufacturer Part Number
LFXP3C-3QN208C
Description
FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O
Manufacturer
Lattice
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP3C-3QN208C
Number Of Macrocells
3000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
136
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3QN208C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFXP3C-3QN208C
Manufacturer:
LOGIC
Quantity:
4
Company:
Part Number:
LFXP3C-3QN208C
Manufacturer:
LATTICE
Quantity:
1 360
Company:
Part Number:
LFXP3C-3QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP3C-3QN208C
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 2-18. Group of Seven PIOs
Figure 2-19. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-20 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
Four PICs
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-16
Buffer
sysIO
Delay
Assigned DQS Pin
LatticeXP Family Data Sheet
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADB “C”
PADB “C”
PADA “T”
PADB “C”
PADA “T”
PADA “T”
PADA “T”
PADB “C”
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
One PIO Pair
Architecture