LFXP3C-3QN208C Lattice, LFXP3C-3QN208C Datasheet - Page 21
![FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O](/photos/16/15/161504/qfp208_sml.jpg)
LFXP3C-3QN208C
Manufacturer Part Number
LFXP3C-3QN208C
Description
FPGA - Field Programmable Gate Array 3.1K LUTS 136 I/O
Manufacturer
Lattice
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP3C-3QN208C
Number Of Macrocells
3000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
136
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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LFXP3C-3QN208C
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Lattice
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LFXP3C-3QN208C
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Quantity:
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Part Number:
LFXP3C-3QN208C
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 2-21. Input Register DDR Waveforms
Figure 2-22. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-23 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
(In DDR Mode)
Delayed
DQS
DQS
D0
D2
DI
DDRCLKPOL
A
ECLK
SCLK
LSR
CE
D
B
2-18
IDDRXB
C
B
A
QA
QB
D
LatticeXP Family Data Sheet
E
D
C
F
Architecture